Global Sources
EE Times-India
Stay in touch with EE Times India
EE Times-India > Processors/DSPs

ECUs for DSP function

Posted: 30 Oct 2008     Print Version  Bookmark and Share

Keywords:FPGA  DSP  ECU  ASICs 

Design engineers in diverse fields such as imaging, communications, multimedia, video applications and mass storage are turning to DSP to enable or enhance a variety of advanced system features. Most engineers use specialised DSP processors for implementing DSP functions such as filters, correlators, sine/cosine building blocks, transforms, and math functions. They are increasingly using traditional FPGAs for DSP functions due to the capability to improve system performance, lower system power dissipation, and integrate more functionality.

Today's FPGA technology is advancing quickly in performance and density, which enables designers to perform billions of multiply and accumulate operations per second. Unfortunately, most of the arithmetic functions use many logic cells, which requires bigger and faster FPGAs. With the larger device usage comes higher power consumption and the need for increased board area.

To overcome these limitations, some designers have begun using standard cell ASICs. These devices are very fast and efficient for arithmetic functions, but lack flexibility for quick design changes, tend to be more costly, and consume too much power, especially for portable applications such as cellular mobile communication and WLAN.

This document describes the use of embedded computational units (ECUs) in QuickLogic FPGAs to implement DSP functions.

View the PDF document for more information.

Comment on "ECUs for DSP function"
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top