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Reduced latency DRAM II clocking strategy

Posted: 13 Oct 2008     Print Version  Bookmark and Share

Keywords:DRAM II  clocking strategy  data storage 

The Micron reduced latency DRAM II (RLDRAM II) addresses the high-bandwidth memory requirements for communication and data storage applications. This is achieved through the use of a flexible clocking strategy that incorporates a series of clock pairs for managing both input and output data. A delay-lock loop (DLL) is utilised to synchronise output data.

The RLDRAM II device requires a differential input master clock pair, CK and CK#, and differential input data clock pairs, DKx and DKx#. The RLDRAM II has output data clock pairs, QKx and QKx# that are derived from the input master clock pair.

This technical note addresses the operation of the device outside the specified range of clock periods and the timing changes that occur in this mode of operation. It also addresses the possibility of running the device within the specified range of tCK with the DLL off (although closing timing could become a concern).

View the PDF document for more information.

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