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Calculating wait states in different access modes and times

Posted: 13 Oct 2008     Print Version  Bookmark and Share

Keywords:Calculating wait states  access times  memory 

The number of wait states for a particular memory device refers to the number of clock cycles that pass before reaching the access time of the device. Data should be accessible after every clock cycle. However, the access time of a memory device may be longer than one clock period. There is a waiting period that includes a number of clock cycles. Given the access time and clock speed, the number of wait states can easily be calculated.

The initial input into the memory device can be read only after an initial access time. This time is typically about 90 ns, depending on the device. The subsequent data access occurs in either burst or page mode.

Burst and page access times are much smaller than initial access times, and are typically about 15 and 30 ns, respectively. During initial access, reading data is triggered by the edge of the clock. The data must stabilise before and after the edge trigger, resulting in setup and hold times. The time it takes from the input change (after the setup time at the clock edge) to the output change because this access time is much larger than one clock cycle. In this case, there is a waiting period of five clock cycles, or wait states.

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