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Cloaking the non-idealities of DC-DC converter stability

Posted: 09 Oct 2008     Print Version  Bookmark and Share

Keywords:power supply circuits  RHP zero  ESR zero  LC compliance 

The main challenge in power supply circuits is guaranteeing stability over a wide range of LC and load combinations. The effects of this variance and the non-idealities of the components manifest themselves in the form of variable LC complex-conjugate poles, LHP ESR zeros, and RHP zeros. Masking the ESR zero by adding a bypass feed-forward path is effective, in spite of slightly increasing the output's response time to fast load-dump events.

Eliminating the RHP zero by introducing an additional phase in the converter cycle to ensure the discharge time is constant, on the other hand, often increases design complexity and power losses to prohibitive levels. Alternatively, sensing the peak output voltage of ESR-dominant converters to mask the RHP zero effects is less costly but narrow in scope, especially when considering low ESR capacitors are growing in popularity. Finally, increasing LC compliance by inserting an LC-servo loop and/or by adding programmability to the filter circuit is necessarily complex and ultimately slow, and especially risky during operating-point transitions. Masking through feed-forward bypass paths may be the most practical solutions...but that depends on the application.

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