Global Sources
EE Times-India
Stay in touch with EE Times India
EE Times-India > Embedded

Avoid design issues with package-aware I/O planning

Posted: 07 Oct 2008     Print Version  Bookmark and Share

Keywords:I/O planning  AFS methodology  package designs  45nm 

Even though companies sell packaged devices and not bare chips, chips are often designed in isolation and may be either overdesigned or too large to fit the package. When chip-level I/O planning is done with no consideration of the package or the rest of the system, the result may be overly complex or unroutable package designs that need multiple iterations to converge.

The problems worsen as process technology advances to 45nm and below and as more functionality is added to silicon. Higher I/O counts running at higher speeds and lower voltages increase demand on the package to meet performance requirements and provide balanced power to the chip. Chip designers must consider package routability, power delivery and I/O behaviour during the initial I/O planning process. To do so, they should combine package-aware I/O planning with automated floor-plan synthesis (AFS), which can be very cost-effective for the chip floor plan and the package layout.

AFS integrates the I/O plan, including bump placement and redistribution layer (RDL) routing, providing features such as automated partitioning and shaping for complex hierarchical designs, congestion-aware hard-macro placement and automated power planning. These capabilities not only save considerable runtime and manual effort, but also provide better timing, area and quality of results. Package-aware I/O planning, when combined with AFS, enables rapid exploration of the design space and provides a faster and more predictable path to design closure.

At the 45nm process node, more chip designs are pad limited, and die sizes are directly affected by how efficiently I/Os are placed and sequenced. Most of the focus on 45nm issues today is within the IP core area of the chip, because that is where the technology will be implemented. Yet the 45nm cores still have to deal with higher voltages, larger geometries and standard interfaces within older devices. Optimised I/O planning and placement thus becomes even more critical.

Importance of I/O planning
Designers migrating to 45nm need design tools that offer guidance on packaging concepts. One methodology gaining acceptance today is package-aware chip design. Just as floor planning is a critical component of SoC design, package-aware I/O planning, as part of the overall system design flow, can help meet cost, performance and time-to-market pressures. I/O planning helps minimise die size through optimised I/O and bump placement and a cost-effective package option. An early package-aware I/O plan combined with AFS gives chip designers a way to analyse the interconnect from the chip's I/O buffers to the PCB.

Within a combined package-aware I/O planning and AFS methodology, it is also critical that the floor-planning tool be able to incorporate the I/O information from the package to drive the placement of the logic on the chip. Magma's Hydra floor-planning tool, helps drive the virtual flat cluster placement of the design, which, in turn, affects how the tool automatically shapes the floor plan and places the macros in each of the blocks. This becomes even more critical with flip-chip designs, where the placement of the bumps will determine how the floor plan is shaped. Hydra can understand the bump placement and RDL routes in its system automatically and come up with the best connectivity to the I/O.

Package considerations can be driven by the logic on the chip. The package engineer should understand the design's restrictions and use that information to come up with the optimal I/O placement and package.

A consideration before implementation is how such a methodology will work in an existing design flow. The design must support industry-standard formats, such as Library Exchange Format/ Design Exchange Format on the chip side and Advanced Package Design on the package side. The software used to implement this methodology must be able to operate in a planning environment in which all the data may not be present and the design may be incomplete. Thus, the extraction, analysis and verification tools must be flexible and smart enough to account for such limitations while providing results that are accurate enough to be useful.

The future direction of package-aware chip design is the same for the package engineer and the design engineer, who both should see the impact of I/O placement on design and package at the same time by working on a unified data model.

With the introduction of automated I/O planning early in the design cycle, I/O performance is enhanced in terms of SI, power integrity, physical implementation and cost. Designers can optimise I/O placement to reduce die size and/or fully use the die area. They can use the least expensive package technology while ensuring that performance targets are met, and get accurate estimates of load conditions to determine driver strength requirements. Perhaps most useful of all, designers can manage chip/package connectivity within the design environment, rather than externally by using a spreadsheet.

Early I/O planning is also useful for package engineers, providing guidance for creating an initial package layout. I/O planning offers a departure from the typical, sequential design of chip and package, enabling a "one-pass" design flow.

The unified data model supports the chip and package as active components in a single user interface. It serves as the repository of the "golden" chip and package interconnect matrix, where chip and package connectivity can be managed. Its capabilities include chip and package trade-off exploration with a feedback metric that details constraints, both electrical and physical. The unified data model facilitates the optimisation process by bringing all design elements into the synthesis flow through the use of the industry-standard OpenAccess database.

The unified data model facilitates optimisation process by bringing all design elements into synthesis flow through the use of the industry-standard OpenAccess database.

Features of a package-aware chip design methodology include I/O synthesis, placement and routing. I/O synthesis creates an optimised I/O plan with cost-effective packaging options, while satisfying physical and electrical constraints. A correct-by-design I/O ring is created to satisfy a set of constraints that include signal/power/ground requirements, package design rules, the core floor plan and board-level I/O requirements.

AFS calculates current requirements of a particular voltage plane based on driver models and calculates the number of balls required. It accommodates each power domain for designs with multiple voltage domains. AFS can optimise the I/O ring plan for minimum die size and I/O row area. If the die size is fixed, it will succeed only if a feasible I/O ring plan exists for it.

I/Os, bumps or bond pads and pins are placed around the periphery of the die by a placement engine before AFS, which considers preplaced instances (I/O and/or the IP core), groupings of I/O cells (such as bus I/Os) and electrical constraints. Once the I/O ring has been synthesised, AFS generates a legal I/O placement.

Package-level routing and voltage domain plane cutting need to be design rule check clean and abide by packaging rules, an important consideration for establishing valid chip-to-package net assignments and proper power plane bump/ball assignments.

Next-generation 45nm design issues are not insignificant. Power/ground I/O planning is more important than ever with lower voltages. Another issue that is already being felt is cross-coupling between the package and the die. At lower voltages, circuitry on the chip is more susceptible to cross-coupling. If the chip and package are not planned together as single circuitry, cross-coupling with the package can severely affect chip performance. This happens when routing on the package passes under the chip. Proscribing routing under a flip-chip die is not practical, and could drive up package cost.

Package-aware chip design, then, must be planned from the start of the project to avoid issues, control cost and realise optimal performance.

Designers migrating to 45nm need not be packaging experts, but they need design methodologies such as package-aware chip design to help them with packaging concepts. Package-aware I/O planning, as part of the overall flow, can help designers meet cost, performance and time-to-market pressures.

- Jayshree Desai
Director of Business Development, Design Implementation Business Unit
  Yukti Rao
Senior Product Manager
Magma Design Automation Inc.

Comment on "Avoid design issues with package-awa..."
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top