Global Sources
EE Times-India
Stay in touch with EE Times India
EE Times-India > Memory/Storage

Effects of capacitive load on read access time

Posted: 30 Sep 2008     Print Version  Bookmark and Share

Keywords:bus standard  input capacitance  capacitive load 

Sometimes a design engineer can be tempted to place multiple devices on the same trace. This is especially true if there is no defined bus standard and reducing costs is critical. However, each of these devices will add its input capacitance to the trace which can cause problems. This application note examines how this added capacitive load effects read access time.

The total capacitive load is defined as the sum of the input capacitance of all the other devices sharing the trace. Note that the capacitance of the device driving the trace is not included. If the total load capacitance on a trace exceeds the output capacitance specification of the driving device then this total load capacitance is defined as 'excessive'. Typically a device input is specified with about 10 [pf] of capacitive load.

View the PDF document for more information.

Comment on "Effects of capacitive load on read a..."
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top