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OMAP processors flash memory interface

Posted: 30 Sep 2008     Print Version  Bookmark and Share

Keywords:EMIF block  flash memory interface  interface modes  OMAP traffic controller 

This application note assumes that the reader is familiar with asynchronous, page and synchronous flash memory timings.

The Texas Instruments OMAP 5912 processor is used as example in this application note. The OMAP 5912, 1510, 1610, 1710, 7xx, and 850 TI OMAP processors use the EMIF block (External Memory Interface) to provide the memory interface; therefore, this information is applicable to these, and most TI OMAP processors.

This application note describes the OMAP processor flash memory interface and the configuration registers that must be programmed to enable the different interface modes, including: configuring the processor and the flash device (if needed) for standard asynchronous operation, asynchronous page mode operation, and synchronous burst mode operation.

The OMAP traffic controller is the central interconnect that manages all accesses to external memories. The EMIF is divided into two distinct function blocks: External Memory Interface Slow (EMIFS), and External Memory Interface Fast (EMIFF). EMIFF provides an external 16-bit interface to SDRAM memories and is irrelevant to this application note. EMIFS is a 16-bit interface to ROM, flash and SRAM memories and is the subject of focus in this application note. Additionally, the signals required to interface to the Spansion flash, the configuration required for the interface, the registers in both the OMAP processor and the flash that need to be programmed, and the interface timing are described.

View the PDF document for more information.

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