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Simulate RFIC designs with substrate parasitics

Posted: 29 Sep 2008     Print Version  Bookmark and Share

Keywords:RFIC designs  substrate parasitics  resistance and capacitance  silicon substrate 

Often, there is a need to simulate RFIC designs with substrate parasitics to accurately represent high-frequency effects in actual silicon. Generally, parasitics appear from a chip's surface layers, especially from metallisation routing and coupling, or from the resistance and capacitance (RC) parasitics of the silicon substrate. Substrate parasitics are especially troublesome when calculating the effects of substrate noise injection and subtle interactions of high frequency ground loops.

For sensitive circuits, such as a voltage-controlled oscillator (VCO) in a PLL, it is important to consider the possibility of substrate parasitic coupling. Nearby digital circuits can inject current into the substrate. However, before substrate parasitics can be simulated in a particular IC process, it is necessary to create a technology extraction file and correlate it to silicon. Once the extraction process is validated, substrate parasitic extraction can become a helpful step in RFIC design.

For GHz-range RFIC designs, it is important to include not only the RC parasitics of metallisation routing, as is done in the MHz frequency range of analogue/mixed-signal circuits, but also to include the parasitics from the substrate. The substrate induces a mechanism of displacement current loss, which would affect the high-frequency performance of a transmission line or a spiral inductor.

The substrate is also a signal-coupling medium. In RF SoC designs, this is a critical factor because noisy digital circuits share the same silicon die as sensitive RF components. It is, therefore, imperative that the physical effects of the substrate are modelled to appropriately determine isolation strategies for the critical components. In the absence of an analytical substrate extraction, designers are left to a trial-and-error noise immunity strategy where potentially undesirable signal coupling through the substrate is not seen until after tape-out.

The RC substrate parasitics are not normally counted. Extracting substrate parasitics is fundamentally easy to do when parasitic modelling is accurate and correlated. However, making the extracted parasitic netlists "simulator-friendly" so that it always converges to a sensible solution is the biggest challenge. This article details the steps to prepare and correlate substrate parasitics for 65nm low-power RF CMOS applications using Cadence QRC Extraction tools. The correlation of test structures to silicon and a case study analysis of a VCO circuit block are discussed.

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