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EE Times-India > EDA/IP

Analogue, mixed-signal connectivity IP at 65nm, below

Posted: 07 May 2007     Print Version  Bookmark and Share

Keywords:IP  CMOS  analogue  mixed-signal 

The demand for sophisticated connectivity IP is increasing as high-speed serial buses such as USB 2.0, PCI Express, SATA, DDR2 and HDMI are widely adopted.

The challenge from the IP provider's viewpoint is to meet analogue performance in a technology that has been targeted for densely packed digital logic. From the SoC integrator's perspective, the IP should be easy to integrate. The IP provider should have already dealt all of the details of creating the IP. The IP should also incorporate new circuit design techniques that accommodate lower supply voltages necessary for portable systems. At the smaller process nodes, design for manufacturing (DFM) must also be taken into account.

This article presents considerations in designing high-performance analogue/mixed-signal circuits with standard deep subµm CMOS technologies.

View the PDF document for more information.

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