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Convolutional coding on configurable processors

Posted: 26 Sep 2008     Print Version  Bookmark and Share

Keywords:error correction  Convolutional coding  DSPs  RISC cores 

One of greatest challenges in communication system design is efficient transmission and reception of information in the presence of errors introduced by the communication channel. The presence of errors is especially pronounced in radio communication, due to the variety of noise sources in the channel. Designers have adopted block coding methods that add redundancy in the encoding of information before transmission. Although the addition of redundant data reduces the overall throughput of the channel, forward error correction improves performance by using the redundant data to correct errors during decoding at the receiver.

Convolutional coding, that is, coding based on time-invariant finite state machines, is widely used in wireless communications. This application note looks briefly at popular techniques for convolutional encoding and decoding, especially Viterbi decoding, and illustrates the power of a configurable processor in handling the performance-intensive signal processing demands of coding and decoding.

Application-specific processors are quickly designed, simulated, built in silicon, and offer significantly better programmability, performance, and power-efficiency than most popular DSPs. In particular, this paper describes user-defined TIE (Tensilica Instruction Extension) instructions which accelerate distance metric calculations, the most performance-critical task in Viterbi decoding, by more than 32 times over most popular DSPs and almost 80 times over most popular 32bit RISC cores.

View the PDF document for more information.





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