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SRAM interface in MIPS32 M4K core for MCU apps

Posted: 25 Sep 2008     Print Version  Bookmark and Share

Keywords:SRAM interface  instruction cache  data cache  interface logic 

MIPS32 M4K core has several features that make it well suited for use in the microcontroller application space. This paper will discuss one of those features: the SRAM interface, which is a standard feature of the MIPS32 M4K core.

The M4K core does not internally support instruction cache (I-cache) or data cache (D-cache) as standard features because of the size and cost restraints in typical MCUs. The MCU environment must fit the maximum number of general purpose IO in the smallest package possible.

What is needed for microcontroller applications is an interface that will allow for tight coupling between the processor core and the memory system with a minimum of interface logic. The MIPS32 M4K core SRAM interface is an excellent solution.

View the PDF document for more information.

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