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MIPS32 M4K core shadow registers for MCU apps

Posted: 25 Sep 2008     Print Version  Bookmark and Share

Keywords:RISC  general purpose registers  32 GPRs  microcontroller 

The RISC architecture brings many advantages to the microcontroller space including the fact that compared to CISC architectures it is much friendlier to compilers and very economical in silicon area. For silicon designers and their target customers, this translates to high performance at low cost.

There are, however, some additional considerations for the end user when using RISC-based processors, especially at the lower frequencies found in the general-purpose MCU space.

One of these issues is related to the context save and restore sequence during an interrupt or exception handling routine. The context save and restore sequence in a RISC-based machine can potentially be very cycle intensive, given that at least 16 if not 32 general purpose registers (GPRs) must be pushed to or popped from a stack or static storage space somewhere in RAM. In some cases, it is only after a significant amount of clock cycles that the core is ready to address the actual interrupt request.

Designers can take shortcuts by not saving all of the registers—either by writing the entire application in assembly language or instructing the compiler to use only certain registers during code translation. Either way, this adds additional constraints to the software design since the software developer must be aware of these requirements at all times.

The MIPS32 M4K RISC core is no different from other RISC cores in this respect in that it has 32 GPRs and an application binary interface (ABI) that uses the full range of the 32 GPRs as defined by the MIPS32 Release 2 architecture.

However, the M4K core provides a more elegant solution in the form of GPR shadow register support, greatly reducing the interrupt response overhead and ultimately matching the highly responsive and deterministic structure of CISC-based MCUs.

View the PDF document for more information.





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