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EE Times-India > EDA/IP

Breaking the gigahertz speed barrier

Posted: 19 Sep 2008     Print Version  Bookmark and Share

Keywords:RTL-to-GDSII  embedded processor  design methodology  synthesisable core 

Traditionally, developing a high performance embedded processor required a custom design methodology, hand-crafted libraries and memories, and a team of specialised layout and circuit designers dedicated to the design and implementation of the processor.

This paper highlights the key "ingredients", investigations and results from a joint MIPS

Technologies/Synopsys project to deliver a high-performance design methodology to end-users. The goal of the project was simple–develop a methodology for the MIPS32 74K synthesisable core that would enable it to achieve processing speeds of 1 GHz or greater, using off-the-shelf 65nm process, standard cells and memories. In this process, the companies identified a number of trade-offs in the design methodology and refined it to produce reliable, high-quality results.

View the PDF document for more information.

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