Global Sources
EE Times-India
EE Times-India > EDA/IP

Structured ASICs with fewer custom masks

Posted: 18 Sep 2008     Print Version  Bookmark and Share

Keywords:ASIC  mask costs  development cost  device cost 

Exorbitant and growing ASIC mask costs require customers to engage in extensive and expensive verification. Designers can expect a full 90nm mask set to cost Rs.4.29 crore ($1 million), but this is only a small portion of the estimated ~Rs.107.15 crore (~$25M) development cost of an ASIC. About half of the overall ~Rs.107.15 crore (~$25M) is devoted to verification tools and engineering intended to increase the likelihood that silicon "works right, first time" and to avoid spending an indeterminate amount of time on analysis and money on masks. Unfortunately a majority of ASIC designs today require re-spins.

This Rs.4.29 crore ($1 million) mask costs will be incurred whether the customer requires only 10 devices for prototyping/experimentation or 10 lakh (1 million) devices for mass production. Therefore, customers cannot embark on an ASIC project unless they are willing to invest the time and money to ensure the masks will be used to produce 100K's of devices. Frankly, there are few opportunities today that, with absolute certainty, will require 5 lakh (500,000) units to provide a justifiable return on investment.

Additionally, silicon foundries are universally moving to 300 mm wafers (from 200 mm) to lower device costs. Since foundries have a minimum number of wafers required for a manufacturing run, and more devices per wafer are manufactured on 300 mm wafers, the minimum number of devices required for a single order increases. Each ASIC purchase transaction needs to be in the 1K's or even 10K's of units depending on the complexity of the device. The prospect of signing up for 10,000 units and committing to Rs.4.29 crore ($1 million) before seeing any silicon is daunting for even the most experienced designers.

One way to minimise this risk is to simply take an existing and well-understood ASIC in an established market and "tweak" it for the new process. But this limits innovation to be merely incremental. To support revolutionary innovation, a methodology involving a silicon prototype that is easy to modify is required. The primary perpetrator for a re-spin by a wide-margin is "Functional Logic Error". Fortunately, this precise issue can be addressed with a prototype. Once the silicon prototype is functionally confirmed, only then does the customer commit to the larger volumes.

View the PDF document for more information.

Comment on "Structured ASICs with fewer custom m..."
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top