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DRAM becomes more exotic

Posted: 16 Sep 2008     Print Version  Bookmark and Share

Keywords:DRAM  56-nm devices  worldine  polysilicon 

Samsung's latest generation of DRAM will enter the market real soon, if it has not yet when this article gets published. At VLSI 2007 Symposium, Samsung promised new materials and structures for 56 nm. Samsung plans to make a number of changes to the basic transistor design—both for the cell access transistor in the memory array and the peripheral support transistors used to design the control logic.

56-nm devices get a "lift" with raised source drains to improve transistor drive current. Micron was actually the first to produce this type of transistor on its 110-nm node DRAM. These earliest Micron raised source/drains were polysilicon. Samsung intends to create a raised source/drain of selective epitaxial growth (SEG) silicon with the elevated portions of the source/drain following the single-crystal silicon structure of the underlying substrate—another Micron first, as its 78 nm already uses a SEG structure. That generation of Micron device also contained the famous recessed channel access transistor, which Samsung has employed since the 90-nm generation. In fact, all manufacturers of stacked capacitor DRAM now use the recessed channel.

Plan view TEM of wordline layout in 68nm Samsung DRAM
Source: Semiconductor Insights

Samsung's first recessed channel device was the RCAT—short for recessed channel array transistor. That design allowed increased channel length in a given piece of chip real estate. Samsung increased the channel length even more by adding a spherical region at the bottom of the transistor trenches. This 68-nm array transistor spawned the S-RCAT acronym, adding the "spherical" prefix.

Samsung will further optimise transistor performance by introducing the dual poly gate process with n+ for NMOS and p+ for PMOS. This promises better effective electrical oxide thickness uniformity and better design margins. This is just one of the techniques, new to high-performance logic devices many nodes ago, finally making their way into commodity memory designs. Nitrided oxides displaced traditional SiO2 for gate dielectrics in the 68 nm Samsung. We need to point out that Elpida led the way in adopting these technologies. Tungsten-clad wordlines, and dual poly gates were both evident in Elpida's 90-nm generation. Nitrided gate dielectrics were introduced by Micron on its 78-nm DRAM.

To improve both wordline resistance and peripheral FET performance, Samsung will add a titanium-nitride barrier between the polysilicon gate layer and the tungsten cap. In older technologies, the tungsten cap layer was intentionally or unavoidably silicided following heat treatment steps. This allows more control over the processing of the wordlines and should reduce variability in wordline resistance. Incidentally, Samsung refers to this as a tungsten wordline, but its 56-nm DRAM will still have a tungsten cap over polysilicon. Elpida introduced this type of wordline structure at 90 nm with a tungsten-nitride barrier between polysilicon and the tungsten cladding.

Samsung DRAM memory

The most interesting innovation to look for on 56 nm will be the metal contacts in the memory array. Samsung promises metal storage node and bitline contacts at 56 nm. Polysilicon plugs are now the norm for transistor and capacitor contacts in the DRAM array for every manufacturer. For several generations, the usual practice has been to use a second and third polysilicon deposition to build up a contact from the access transistor's source or drain down at the substrate up to either the tungsten bitline or the storage node of the capacitor. Over the years, polysilicon plugs for array transistor contacts were better-suited to high-density self aligned structures. Transistor source/drain regions are formed by outdiffusion of dopants from the highly doped polysilicon.

Tungsten provides lower resistance, which is why it's used just about everywhere else in the industry—including the contacts to peripheral FETs in a DRAM. Switching to a metal contact process will shave a few steps off the current DRAM process. Samsung reports that the breakdown voltage for transistors with metal contacts is comparable with those seen with polysilicon plug contacts in a similar configuration while cutting contact resistance in half.

56-nm production will add immersion lithography to the mix of ArF and reticle enhancement techniques used today. Semiconductor Insights' latest analysis detected a 61-nm half-pitch of active area patterning proving that Samsung already employs double patterning at the OD level of its 68-nm device. There was a lot of hype about Intel using double patterning on its 45-nm high-k, metal gate process introduced on the Penryn microprocessor, but it was already in use for this DRAM packaged five weeks before the Intel Penryn unit. The only choice for further reductions to the critical dimensions in the active area design was for Samsung to add immersion optics to its lithography tools for 56 nm.

The critical limit to shrinking a DRAM design is how leaky the access transistor is compared with how much charge the capacitor can store. Semiconductor Insights extracted a complete set of transistor performance data from the 68-nm S-RCAT. Leakage measured 2.5nA/µm at room temperature. Zirconium-oxide was the primary dielectric on the 68nm capacitor. At VLSI 2007, Samsung described a zirconium-oxide/aluminium-oxide/zirconium-oxide or "ZAZ" triple layer dielectric for 56 nm. In fact, the 68-nm capacitor dielectric was similar to the ZAZ structure. Samsung has been playing around a lot with capacitor dielectrics from node to node. Prior to zirconium-oxide at 68 nm, aluminium-hafnium-oxide outer layers sandwiched a central layer of aluminium-oxide for the company's 80-nm device.

Samsung achieved 10.4 Mb/mm2 at 80 nm and improved that to 14.7 Mb/mm2 at 68 nm. Based on the projections and an expected cell size of 0.019µm2, we can expect to see the 56-nm generation of DRAM reach 20 Mb/mm2 squeezing 2Gb onto a single die.

It would be unwise to doubt Samsung's ability to continue on this density path. It aggressively scaled sense amp transistor gate lengths from 0.22µm to 0.12µm in the move from 80 nm to 68 nm. With the raised source/drain transistor at 56 nm, Samsung reported NMOS drive current of 440µA/µm. That performance level will give designers the option of continuing to reduce area or optimise for higher performance.

When 56-nm DRAM finally hits the street, Semiconductor Insights will confirm what Samsung has claimed. Beyond the straightforward structures like metal contacts and tungsten-clad wordlines, our upcoming investigation will check key details Samsung mentioned in its VLSI 2007 paper. We will test the access transistor drive current and leakage performance with nanoprobing. We will also provide 2-D carrier profiling of the S-RCAT with scanning capacitance microscopy to reveal the technology enabling Samsung's claimed drive current improvements.

Beyond 56 nm, we can look forward to a brave new world in DRAM. Samsung was the first to introduce a 3-D transistor when the 90-nm DRAM launched the RCAT structure. Samsung's countrymen at Hynix produce a similar device. But at VLSI this year, Hynix announced it will be going a step further with the 3-D transistor we have heard everyone talking about for years—the FinFET. Samsung presented a FinFET for flash at the 32-nm node. Based on this, expect to see the very first FinFET's in Hynix DRAM, followed by Samsung flash chips.

- Don Scansen
EE Times





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