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Intel, Microsoft present parallel progress

Posted: 27 Aug 2008     Print Version  Bookmark and Share

Keywords:parallel programming model  multi-core processor  system software stack  computer interfaces 

Intel Corp. and Microsoft Corp. are taking small steps on the long road to creating a new parallel programming model for tomorrow's multi-core processors. During the Intel Developer Forum, the companies discussed their progress in different presentations.

Microsoft talked about its vision for adding new layers to its system software stack as well as point extensions it is making to its .Net environment. Intel discussed new planned extensions to the x86 instruction set and showed progress on Ct, extensions to the C++ language aimed at supporting greater parallelism.

From the advent of computing, software got a free ride as Moore's Law drove serial processors to greater performance levels. But growing problems of power leakage in microprocessors has driven a shift to putting more cores on a die, forcing a historic transition to a parallel programming model yet to be invented, said David Callahan, who leads Microsoft's Parallel Computing Initiative, announced late last year.

Microsoft and Intel are backing various academic research initiatives to help plough the way forward. At IDF, they shared some of the progress from their internal corporate teams.

As if this job was not ambitious enough, Microsoft hopes to use the parallel shift to enable advances in computer interfaces.

"This is really about a new set of natural and immersive experiences we want to deliver," said Callahan. "The parallel computing shift is just a sort of accident along the way."

The underlying software plumbing needs an overhaul before such work can begin. Callahan said tomorrow's system software will be much more layered into separate elements including new runtime environments that sit in a user space below application libraries and above hypervisors and the core operating system kernel.

The runtime environments will act as schedulers, working cooperatively with hypervisors that map virtual to physical resources and OSes that manage access to physical hardware. "This represents a refactoring of traditional OS services," said Callahan.

The aim is to better handle the growing number of competing requests in multi-core environments. Even today's PCs host a "terrifying number" of processes running in parallel, creating sequential-processing bottlenecks and losses in data locality, he said.

Microsoft will expose its runtime layer to third parties including Intel because it expects there will be a need for many kinds of interoperable software abstractions from different vendors to serve different application types. Tomorrow's software also calls for improved techniques in cooperative scheduling, better thread-level performance and enhanced message passing.

"There are a deep set of changes before you can even get to rebuilding libraries and rewriting apps," said Callahan.

"This is an ambitious shift, and this is just their first cut at it," said Michael McCool, chief scientist at RapidMind, which sells parallel programming tools for the x86 and other processors.

"Initially they have done some of the obvious things supporting parallel tasks, but I haven't seen anything about efforts to abstract data," McCool added.

Tomorrow's parallel programming model will need new categories for sorting data so it can be marshaled into appropriate locations in cache at the right time, said McCool. He noted that Intel's latest high speed processor interconnect significantly reduces latency, but if the wrong data appears in cache, latency can shoot up dramatically.

In the area of programming tools, Callahan said Microsoft is making extensions to its .Net environment based on its C# 3.0 language. Intel said it will release beta version of four new parallel programming tools in November.

Programmers will need a whole new tool set to help debug, optimise and validate parallel code, Callahan said. Debugging has to move from single-step to visualisation tools that capture trends in thousands of synchronised tasks, said McCool.

On the language front, Intel talked about Ct, an extension of C++ for multi-core processors. The language aims to automate the job of splitting processing tasks across a number of cores without the programmer needing to know the details of the underlying x86 architecture.

The language delivers 1.7 to 3.7 times performance speed ups on code running on four processor systems, according to data shown by Anwar Ghuloum, a principal engineer in Intel's corporate technology group. Ct was initially targeted at Intel's general purposed Nehalem quad core chips, but is now up and running on its prototype 16-core Larrabee graphics processors as well.

"RapidMind and Ct are pointing in the same direction, but we have been around longer as a mature commercial offering while Ct is still essentially a research API," said McCool.

Intel also discussed its Advanced Vector Extensions (AVX), instruction set extensions that will replace the Streaming SIMD Extensions currently used in its processors.

AVX is expected to provide a superior environment for parallel programming compared to SSE, boosting floating point performance and adding wider single instruction, multiple data (SIMD) units. However it is not expected to be fully implemented until Intel's SandyBridge processors, a 32nm processor family debuting probably in 2010, a full two generations out from today' Nehalem CPUs.

Separately, Intel disclosed a new feature in its Nehalem processors to optimise performance when some of cores are not being used. The feature can automatically shut off one or more cores when they are not being used and bolster the amount of chip-level power available to the remaining cores that are running.

The technique involves a new transistor design with high-off resistance that helps reduce even the leakage current from a core that is turned off. It also employs a million-transistor controller and sensors on the processor.

"The more powder constrained you are, the bigger the performance boost," said Rajesh Kumar, an Intel fellow heading up power management on Nehalem.

Archrival Advanced Micro Devices has had a capability to run cores independently via separate power planes on its processors. Previously Intel had said such features do not result in significant savings in power.

- Rick Merritt
EE Times

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