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Standard improves AMS design

Posted: 26 Aug 2008     Print Version  Bookmark and Share

Keywords:Verilog-Analogue Mixed-Signal  Verilog-AMS 2.3  mixed-signal design  simulation 

Accellera has announced that its Board of Directors and Technical Committee members approved a new version of its Verilog-Analogue Mixed-Signal (AMS) standard, Verilog-AMS 2.3, as an Accellera standard for analogue and mixed-signal design and simulation. The new Verilog-AMS standard unifies the Verilog-AMS 2.2 specification with the IEEE Std. 1364-2005 or Verilog hardware description language (HDL) standard.

Verilog-AMS 2.3 enables users to develop standard and tightly integrated Verilog-AMS modules and allows EDA software tool developers to implement EDA tools without ambiguities in the language interpretation.

Verilog-AMS 2.3 encompasses analogue and mixed-signal extensions to IEEE Std. 1364, which is widely used today for digital circuit design and verification.

"A unified Verilog-AMS language integrated with the IEEE Verilog standard improves AMS design and will result in an increased acceptance of the standard," said Shrenik Mehta, Accellera chairman.

Apart from IEEE-1364 integration, Verilog-AMS 2.3 introduces new analogue and mixed-signal features to support and enable improved top-down AMS design and verification methodologies. These include enhancements to table_model, support for multiple analogue blocks, and resolution of language conflicts with the SystemVerilog IEEE Std. P1800, such as, changing the digital domain name to 'discrete' from 'logic' as logic is a keyword in SystemVerilog, and making the usage of array literals consistent.

The next phase of Accellera's AMS technical activities will include integration of the AMS standard with the SystemVerilog language, IEEE Std. P1800, and extensions to the AMS language for mixed-signal assertions and behavioural modelling support.

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