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Memory designs to rely on FBCs

Posted: 21 Aug 2008     Print Version  Bookmark and Share

Keywords:floating-body cells  silicon-on-insulator  DRAM  cache memory 

During the 2008 Symposium on VLSI technology in Hawaii, Intel Corp. revisited its research on floating-body cells (FBCs) for advanced cache designs in microprocessors. The big question is whether Intel is finally endorsing silicon-on-insulator (SOI) technology, as the company described the world's smallest FBC-based planar device on SOI for possible use at the 15nm node. In a related paper, Intel described adaptive circuit techniques for SRAM cache cells. Both technologies are still in the R&D stage.

Waiting in the wings in the race towards FBCs—also called floating-body RAMs (FB-RAMs)—is Intel rival Advanced Micro Devices Inc. Two years ago, AMD licensed an embedded FBC technology from Innovative Silicon Inc. (ISI).

For years, FBC has been touted as an alternative to conventional cache memory, because current capacitor-based technology is running out of gas. FBC is a candidate for increased memory density, compared with the standard six transistor (6T) cache memory used on all microprocessors today.

New architecture needed
"In a standard DRAM, there is a capacitor and a transistor," according to ISI. "The capacitor stores the logic state, 1 or 0, and the transistor provides the rest of the circuitry access to the capacitor. To read a DRAM cell, the transistor is turned on and the charge on the capacitor is allowed to flow onto a bitline, creating a small voltage, which can then be detected."

Jeff Lewis, VP of marketing at ISI, warned that some major issues with the capacitor in DRAMs are prompting the need for a new architecture. "Capacitor scaling is becoming almost impossible," Lewis said in an interview at this year's Design Automation Conference.

Lewis speculated that there are possibly "one or two generations left in DRAM scaling," which may spur the need for an FBC in memory designs. But he also said there are some issues with FBC technology. "Bringing in a new memory technology is a challenge," he said.

In general terms, FB-RAM eliminates the need for the capacitor used in conventional DRAM bit cells built in bulk silicon. In bulk CMOS, the charge that forms a transistor's body is tied to a fixed voltage. In SOI, the untied body is suspended in silicon above the thick oxide layer. To make the floating body behave like a capacitor, a carefully controlled voltage is applied on both sides of the body.

FBC technology enables three to four times the bits compared with traditional embedded memory in cache designs, said Mike Mayberry, VP of the technology and manufacturing group and director of components research at Intel. That, in turn, speeds up computational rates, Mayberry said during a conference call.

Using SOI
In 2006, Intel discussed dual-gate transistor architecture for research purposes that used FBC technology. At VLSI, the chip giant described a planar architecture using SOI, in somewhat of a reversal from its previous stance. Unlike rivals AMD and IBM, which use SOI in processor designs, Intel has dismissed the need to use the technology in mainstream production.

"The FBC is a planar device on SOI, but the film thicknesses are very different from what is considered conventional SOI," according to Intel. "For example, the buried oxide thickness is only 10nm, compared with >100nm for most common SOI implementations. That means an SOI design for a thick bottom oxide (BOX) won't work on thin BOX and vice versa. This is one of many integration issues that need to be resolved before we can choose a technology option."

In a paper titled "A Scaled Floating-Body Cell Memory with High-k + Metal Gate on Thin Silicon and Thin BOX for 15nm Node and Beyond," Intel detailed the world's smallest FBC-based planar devices, with functional parts measuring down to 30nm gate lengths. Intel's devices are two generations smaller than similar components described in other published work, Mayberry said.

FB-RAM eliminates the capacitor used in DRAM bit cells built in bulk silicon.

In its paper, Intel said: "The devices with 60nm gates show suitable memory retention, and, at this dimension, a bit cell could be less than 0.01m2 in size, making it suitable for potential use at the 15nm node.

There is also excellent agreement between device and simulation that allows prediction of continued scaling to the 10nm technology node."

Lowering SRAM voltage
In a related paper, the company took another route. "This paper demonstrates new adaptive circuit techniques that would allow lowering the minimum operating supply voltage of SRAM cache cells by making the cells more tolerant to variations in process, voltage, and temperature," Intel said.

"Under certain operating conditions, measurements on a 45nm test-chip show that number of single cell errors is reduced by as much as 26x. These circuits could allow Intel to push to better performance and power characteristics without failures on future processes," according to the chip giant.

Not to be outdone, AMD two years ago licensed floating-body SOI memory developed by ISI, which has been touting Z-RAM (zero capacitor) technology for use in memory and microprocessors. AMD is reportedly looking at the technology for larger, on-board L3 caches. AMD did not respond to e-mails on the subject.

South Korea's Hynix Semiconductor Inc. is also a licensee of Z-RAM. But both AMD and Hynix have yet to roll out products based on the technology.

- Mark LaPedus
EE Times

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