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'Smallest' SRAM bit cell debuts

Posted: 20 Aug 2008     Print Version  Bookmark and Share

Keywords:SRAM  SRAM bit cells  22nm design  six-transistor design 

IBM Research claims to have fabricated the world's smallest SRAM bit cell with joint industry and university development partners. The SRAM bit cell, which was cast using 22nm design rules, measures just 0.1µ2.

The SRAM was developed with partners AMD, Freescale, STMicroelectronics, Toshiba and the University of Albany's College of Nanoscale Science and Engineering.

The previous world record for the smallest SRAM bit cell was established by IBM in 2004 at 0.143µ2 in an experimental 32nm device. Since then, several engineering groups have questioned whether conventional architectures could be extended to the 22nm node. IBM researchers assert than it can.

"Before the introduction of high-k metal gates, many questioned whether conventional device architectures could be extended to 22nm, but now we have demonstrated that conventional scaling will still work," said Mukesh Khare, project manager at IBM Microelectronics.

"Our gate lengths were less than 25nm, which was considered impossible just a few years ago," Khare said.

IBM was able to shrink the main features of its 22nm transistors, the gate length, the spacers and the contact that sits between adjacent gates, and demonstrated that the devices can still be turned off, which was a major stumbling block in previous attempts at shrinking SRAM bit cells smaller than 0.143µ2.

Unlike earlier versions,,the current 0.1µ2 SRAM bit cells can be fabricated using tools appropriate for mass production.

"Our previous world record for smallest SRAM cell used e-beam lithography, which was a major achievement at the time. But is not a production tool. You can only fabricate about six wafers a day using e-beam lithography," said Bruce Doris, 22nm device manager at IBM research. "We used conventional high-numerical-aperture immersion lithography."

The SRAM bit cells were fabricated at IBM's 300mm research facility in Albany using a conventional six-transistor design. The experimental 22nm device is two-generations removed from commercialisation (IBM and its partners are currently manufacturing commercial devices at the 45nm node). Before moving to 22nm, the partners said they plan use high-k dielectrics and metal gates at 32nm for what they say is the first time.

To fabricate the 22nm device, IBM and its partners used immersion lithography, high-k dielectrics and metal gate stacks. The transistors had gate lengths of less than 25nm, used thin spacers, co-implants, very thin silicides and damascene copper contacts.

Details of the new SRAM bit cells will be announced during the International Electron Devices Meeting in San Francisco in December.

- R. Colin Johnson
EE Times





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