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BeSang enables first 3D IC

Posted: 13 Aug 2008     Print Version  Bookmark and Share

Keywords:3D chip  licensing  demonstration chips  memory circuitry 

The world's first 3D chip process is ready for licensing from BeSang Inc.

BeSang fabricated demonstration chips with 12.8 crore (128 million) vertical transistors for memory bit cells above their control logic. The chips were designed at the National Nanofab Centre (Daejeon, South Korea) and Stanford Nanofab. BeSang said its process, which is protected by over 25 patent applications, will allow flash, DRAM and SRAM to be placed atop logic, microprocessor cores and SoCs.

BeSang claims it achieved 3D by fabricating logic circuitry using a high-temperature process on the bottom and by fabricating memory circuitry using a low-temperature process on top of the logic. By placing logic and memory on different layers of the same 3D chip, BeSang's process packs in more die per wafer, which translates into lower costs per die.

"BeSang was founded five years ago to work on 3D IC technology," said Sang-Yun Lee, BeSang's founder and CEO. BeSang "has introduced a single-chip 3D IC process that is ready for commercialisation. By using a low-temperature process and orienting vertical memory devices on top of logic devices, we make more dies per wafer, and that is how the cost per die goes down."

At BeSang ("flying high" in Korean) Lee perfected the first true 3D IC process with former Samsung engineer Junil Park, developer of the first atomic layer deposition tool for high-k dielectrics. Because the new IC processing technique does not stack dies, the company claims normal cooling techniques will work, for no additional heat is generated by its slightly thicker 3D chips.

Current planar (2D) chips that contain memory must surround their memory arrays with logic circuitry to address bits and to perform logic functions. Placing memory and logic alongside each other forces the use of long interconnection lines between the two.

BeSang, on the other hand, placed logic circuitry on the bottom layer and the memory bit cells on the higher layers of the 3D chip, enabling very compact designs with very short interconnection lines between them.

Prior to BeSang's design, "all the previous attempts were pseudo 3D," said Simon Sze, who co-invented the floating-gate transistor for nonvolatile memory cells in 1967 at Bell Labs. Sze is now a professor at the National Chiao Tung University in Taiwan.

"SoC put logic alongside memory on the same chip, but have had to compromise on performance since both were fabricated with the same process. By putting the memory devices on top of the logic devices, using separately optimised processes, BeSang is increasing density without compromising performance."

BeSang's process works by first fabricating the logic on one wafer with normal vias and interconnection layers. Then memory devices are fabricated separately on a donor wafer, and the two wafers are aligned and bonded to form a single 3D unit.

Because logic and memory are processed on different wafers, both can use normal 850°C processes that have been separately optimised. The two wafers are then sent to another line, where they are precisely aligned and bonded using a proprietary low-temperature, 400°C process.

The donor wafer essentially contains one vertically oriented bit cell, which, after bonding, is etched into millions of pillar-shaped transistors that control individual bit cells. The final step interconnects the individual bit cells and caps the 3D wafer with final metallisation layers.

"The cost of BeSang's 3D chips should be much lower, because you are reducing the overall chip area by putting all your logic in one process on the bottom wafer, putting all of your memory, using a different process, on the top wafer, and using the conventional vias to interconnect them," Sze predicted.

Demonstration chips were processed on 8-inch wafers using 180nm CMOS technologies. The test chip contains 12.8 crore (128 million) vertical transistors suitable for fabricating flash, DRAM or SRAM memory cells atop logic circuits. The bottom layer of logic was separated from the upper memory layer by single-crystal silicon, and two metal interconnection layers containing the vias between logic and memory. The top memory layer was lifted from the memory donor wafer, which contained alternating layers of n- and p-type semiconductors. The donor wafer was reused four times, each time allowing one big vertical n-p-n transistor to be deposited atop the logic wafer.

After etching individual vertical transistors for bit cells, an additional metal interconnection layer capped the 3D wafer before dicing.

- R. Colin Johnson
EE Times

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