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Row boundary crossing functionality in CellularRAM memory

Posted: 13 Aug 2008     Print Version  Bookmark and Share

Keywords:CellularRAM  memory controllers  boundary crossings  row boundary crossing 

Micron's CellularRAM devices are designed to be backward-compatible with 6T SRAM and early-generation asynchronous and page PSRAM, and are based on a fixed row size. Memory controllers must handle boundary crossings between consecutive rows. This technical note describes the conditions that exist at the row boundary for the WAIT pin and burst READ/WRITE operations, focusing on row boundary crossing (RBC) as supported on CR 1.0-compliant devices.

When a memory controller attempts burst READ/WRITE operations across an RBC, the main areas to consider are:

- An RBC burst WRITE will be successful if CE# is asserted for (2LC + 1) when the row crossing occurs.

- The WAIT pin indicates when the RBC occurs so the memory controller can take the appropriate action.

- The WAIT pin operation will vary depending on the settings in BCR[8] and BCR[10].

View the PDF document for more information.

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