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Multibit interfaces boost serial flash memory

Posted: 05 Aug 2008     Print Version  Bookmark and Share

Keywords:serial flash  multi-bit interfaces  serial peripheral interface  execute-in-place 

The demand for serial flash memory continues to rise as designers of digital TVs, DVDs, PCs, modems, printers and mobile consumer electronics devices view the memory as an increasingly attractive code execution alternative to parallel NOR flash. "We think the market will jump from about Rs.2,397.96 crore ($560 million) last year to more than Rs.4,282.07 crore ($1 billion) this year as conversion from parallel to serial begins moving up to the 16- and 32-Mbit devices," said Alan Niebel, CEO of Web-Feet Research.

Driving increased demand are the memory's multiple advantages in terms of lower pin count, reduced board space, lower power and reduced system cost. In a standard eight-pin SO package, flash memories using the standard serial peripheral interface (SPI) need up to 80 per cent less board space than a parallel flash in a typical 32-pin or larger PLCC.

Just as important is a serial flash memory's impact on design complexity. Whereas a typical 32-Mbit parallel flash requires 21 address lines, 16 data lines and three control lines between the MCU or ASIC and the memory, a 32-Mbit serial flash requires just two data and two control lines. Controllers with higher pin counts require more board layers for signal routing, and the more pins the controller devotes to system memory, the fewer pins are available to deliver the processing power and memory bandwidth needed to support new features.

To meet growing demand, serial flash suppliers Atmel, Macronix, Numonyx, Silicon Storage Technology (SST), Spansion and Winbond are offering higher-density devices. Spansion last year announced a 128-Mbit SPI flash IC using its 90-nm MirrorBit technology. But analysts say the real move to new applications will come with the arrival of devices featuring multi-bit interfaces.

Most initial serial flash deployments have focused on execute-in-place (XiP) applications. To execute these programs directly from memory, designers use NOR flash, which can be addressed as individual words. But the performance limitations of the traditional, single-bit SPI interface have forced designers in many applications to couple SPI-based serial flash with shadow RAM (usually an SRAM) to support faster access.

To overcome this limitation, eliminate the cost of the SRAM and improve boot time, several vendors have introduced devices equipped with multi-bit interfaces. Last August, Winbond Electronics Corp. introduced what it said was the first quad-SPI serial flash memory IC. The 16-Mbit memory, the first in a family of devices that will range up to 64 Mbits, offers single, dual and quad I/Os in a compact, eight-pin SOP. Supporting clock rates to 80 MHz, the device enables equivalent clock frequencies up to 320 MHz in quad-SPI mode, or more than six times the transfer rate of a standard serial flash memory running at 50 MHz. Random access overhead is cut by more than 70 per cent by shrinking the number of clocks needed per read instruction from 40 to 12. Winbond claims that in a typical instruction fetch of 32 bytes, the quad device is capable of access rates of better than 32 MB/s—roughly 50 per cent better than a comparable parallel flash with 70-ns access and 100-ns cycle times.

- John H. Mayer
EE Times

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