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EE Times-India > EDA/IP

How to achieve fast timing closure on FPGA designs

Posted: 01 Mar 2006     Print Version  Bookmark and Share

Keywords:FPGA design  physical synthesis  timing closure 

The article discusses the difficulties of implementing physical synthesis for FPGAs by contrasting FPGA with ASIC technologies. The benefits of physical synthesis are shown in the context of understanding the limits of conventional synthesis when applied to an FPGA design. Pushbutton synthesis verses design planning is also discussed.

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