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Specs on 3D chip stacks released

Posted: 14 Jul 2008     Print Version  Bookmark and Share

Keywords:3D stacking  memory chips  processor die  memory 

The Intimate Memory Interconnect Standard (IMIS) being promoted by the 3D-IC Alliance recently released its official specification for 3D stacking memory chips.

Founding members of the Alliance, Tezzaron Semiconductor Corp. and Ziptronix Inc., are already fabricating memory chips using the IMIS port, the first versions of which will be available by the end of 2008.

"Today's high-speed processor cores need 3D interconnect with very high sustained bandwidth that is beyond any existing or planned DDR memory technology," said Robert Patti, CEO, Tezzaron.

Owing to the low capacitance of the "intimate" connection achieved by stacking a memory die atop a processor die, power consumption is about 24µW/pin compared to 30mW to 40mW per pin for DDR. That low-power in IMIS's 1,000-pin parallel connection between processor and memory limits power consumption to less that 3W, compared to over 30W for conventional interconnects.

"We believe that IMIS solves the processor makers' bandwidth problems to [achieving] multi-gigabit memories—typical access times to our DRAMs is seven nanoseconds," said Patti. "We are getting DRAM densities at near SRAM speeds and better than DRAM costs."

The IMIS port measures 450µ by 2,000µ and contains a pin grid that is 19 cells high by 80 cells wide, each cell measuring 25µ2. Processor manufacturers modifying their dies to include an IMIS port will be able to add compatible memory chips from any member of the 3D-IC Alliance, which includes about a half dozen members.

- R. Colin Johnson
EE Times

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