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ADC delivers highest signal-to-noise ratio

Posted: 25 Jun 2008     Print Version  Bookmark and Share

Keywords:analogue-to-digital converter  low-jitter  clock synthesiser  signal-to-noise ratio 

Texas Instruments Inc. today introduced a 16-bit, single-channel, 135 mega samples per second (MSPS) analogue-to-digital converter (ADC) and a low-jitter clock synthesiser. The combined signal chain solution provides unmatched dynamic system-level performance in applications in the field of communications, defence, and test and measurement. The data converter and clock are available on the same evaluation module (EVM) to facilitate fast evaluations of these complex systems.

signal chain solution

Low noise enhances performance in wide-bandwidth applications

The ADS5483 ADC has the industry's highest signal-to-noise ratio (SNR) and spurious free dynamic range (SFDR) over comparable ADCs on the market, for input frequencies from DC through the second Nyquist zone, according to the company. Sampling at 135 MSPS, the ADC can achieve a SNR of 78.6 dBFS with 95 dBc SFDR for a 70-MHz input frequency (IF), which is up to 3.5 dB greater SNR or 8 dB greater SFDR over comparable ADCs. The higher performance of the ADS5483 increases design flexibility and benefits many applications. For example, it offers greater accuracy for test and measurement systems and higher sensitivity with larger bandwidths in wireless communication including air interfaces, such as WCDMA, TD-SCDMA, WiMAX, LTE and multi-carrier 3GSM.

In wide-bandwidth applications, the ADS5483 eases analogue front-end design by incorporating a fully differential input buffer. Developed in TI's BiCom3 high-speed process technology, this buffer provides constant input impedance over input frequency and eliminates kickback from the ADC's track-and-hold structure to ensure consistent linearity of the signal. In addition, unlike competitive ADCs, the ADS5483 utilises differential double data rate (DDR) LVDS outputs to significantly reduce the number of I/O traces and pins it consumes on FPGA or ASIC devices.

Highly flexible clock enables system-level performance

The ultra-low jitter CDCE72010 clock synthesiser provides best-in-class additive jitter performance at less than 50 femtoseconds (fs), which meets the jitter requirements to clock high-speed ADCs, such as the ADS5483. For example, the combined EVM using the CDCE72010 and a crystal band pass filter to drive the ADS5483 at 122.8 MSPS achieves a high system-level SNR of 78.0 dBFS SNR and 89.1 dBc SFDR with a 100-MHz input frequency.

The new clock synthesiser can accommodate a wide range of frequencies to meet the requirements of various systems. It can support up to 10 LVPECL, 10 LVDS or 20 LVCMOS configurable outputs at frequencies up to 1.5 GHz and input frequencies from 8kHz up to 500 MHz. Designers can integrate two frequency sets within one clock synthesiser with the option of two external VCO/VCXOs. The CDCE72010's on-chip EEPROM stores default settings, which allows designers to reduce system start-up time and eliminates the need for an external component.

Tools and signal chain solutions ease development and enable rapid evaluation

The ADS5483 and the CDCE72010 are available on the same EVM to facilitate fast evaluations of complex systems. To provide designers with frequency planning flexibility, the EVM includes an open socket for the VCXO and crystal filter as well as bypass for an external source clock input.


Availability and packaging

The ADS5483 and CDCE72010 are both available today in QFN-64 PowerPAD packages. Pricing in quantities of 1,000 is Rs.2,601.37 ($65.00) for the ADS5483 and Rs.438.23 ($10.95) for the CDCE72010.

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