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System level design considerations when using I2C serial EEPROM devices

Posted: 15 Dec 2004     Print Version  Bookmark and Share

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) 1999 Microchip Technology Inc. DS00709B-page 1

M AN709

INTRODUCTION

Developing systems that implement the I2C protocol for

communicating with serial EEPROM devices requires

that a certain key factors be considered during the

hardware and software development phase if the sys-

tem is to achieve maximum compatibility and robust-

ness. This application note discusses these factors,

both hardware and software, to help insure that an opti-

mal system design is achieved. This application note is

limited to single master systems and therefore does not

specifically address the unique requirements of a multi-

master system. However, the concepts presented in

this application note apply equally as well to those sys-

tems.

CONDITIONS TO BE CONSIDERED

Due to the bi-directional nature of the data bus devices

operate in both transmit and receive modes at various

times. In order to make this bi-directional operation

possible the protocol must define specific times at

which any given device may transmit or receive, as well

as define specific points in the protocol where the func-

tions are swapped (i.e. the transmitter becomes the

receiver and the receiver becomes the transmitter).

There are a number of events which could potentially

cause this sender/receiver `synchronization' to be lost,

which can result in situations where:

7 Both the master and the slave are in a send

mode.

7 Both the master and the slave are in a receive

mode.

7 The `bit count' is off by one or more bits between

the master and the slave.

These events, which include the microcontroller being

reset during I2C communication, brown-out conditions,

excessive noise on the clock or data lines, and

improper bus input levels during power up, can be

effectively neutralized through a combination of hard-

ware and software techniques.

FIGURE 1: RECOMMENDED HARDWARE

CONFIGURATION

INSURING `BUS-FREE' DURING

POWER-UP

In order to insure that the internal state machine of the

serial EEPROM is correctly initialized at power up, it is

crucial to guarantee that the device sees a `bus-free'

condition (defined as both SCL and SDA being high)

until VDDmin has been reached. The ideal way to guar-

antee this is through the use of pull-up resistors on both

the SDA and SCL lines. In addition, these pull-ups

should be tied to the same voltage source as the VDD

pin of the device. In other words is the device VDD is

supplied from the main positive supply rail then the

SCL and SDA pull-ups should be connected to that

same supply rail (as opposed to being connected to a

microcontroller I/O pin, for example). Figure 1 is an

example of the recommended hardware configuration.

The reasoning behind doing this is the same for both

adding the pull-up to the SCL line and for utilizing the

same supply for the VDD pin and the pull-ups. As any-

one who has had any experience with CMOS logic

already knows, it is necessary to ensure that all inputs

are tied either high or low, since allowing a CMOS input

to float can lead to a number of problems. If the SCL

line does not have a pull-up, or if the pull-ups are not

tied to the VDD supply rail, then conditions occur, how-

ever briefly, where the SCL/SDA inputs are floating with

respect to the VDD supply voltage. When possible this

condition should be avoided.

Author: Rick Stoneking

Microchip Technology Inc.

EEPROM

5C

SCL

SDA

VDD

System Level Design Considerations When Using

I2CTM Serial EEPROM Devices

I2C is a trademark of Philips Semiconductors

AN709

DS00709B-page 2 ) 1999 Microchip Technology Inc.

When it is not possible to add a pullup resistor to the

SCL line (i.e. the hardware design has already been

finalized) then the firmware should be configured to

either: 1) drive the SCL line high during power up or,

2) float the SCL input during power up.

Of these two options, the first is the recommended

method, despite typical concerns regarding latch-up,

because it does not negatively impact the battery life in bat-

tery powered applications. Microchip Technology's serial

EEPROM devices, like all CMOS devices, are susceptible

to latch-up, however latch-up does not occur until currents

in excess of 100mA are injected into the pin.Typical micro-

controllers are not capable of supply currents of this mag-

nitude, therefore the risk of latch-up is extremely low.

The second option is also acceptable but does lead to

a brief increase in the current draw of the device during

the time period in which the SCL pin is floating with

respect to VDD.This increase can be significant in com-

parison to the normal standby current of the device and

can have a detrimental affect on battery life in power

sensitive applications.

In all cases it is important that the SCL and SDA lines

not be actively held low while the EEPROM device is

powered up. This can have an indeterminable effect on

the internal state machine and, in some cases, the

state machine may fail to correctly initialize and the

EEPROM will power up in an incorrect state.

Another improper practice which should be pointed out is

the driving of the SDA line high by the microcontroller pin

rather than tri-stating the pin and allowing the requisite

pullup resistor to pull the bus up to the high state. While

this practice would appear harmless enough, and indeed

it is as long as the microcontroller and EEPROM device

never get out of sync, there is a potential for a high cur-

rent situation to occur. In the event that the microcontrol-

ler and EEPROM should get out of sync, and the

EEPROM is outputting a `low' (i.e. sending an ACK or

driving a data bit of `0') while the microcontroller is driving

a high then a low impedance path between VDD and VSS

is created and excessive current will flow out of the micro-

controller I/O pin and into the EEPROM SDA pin. The

amount of current that flows is limited only by the IOL

specification of the microcontoller's I/O pin.This high cur-

rent state can obviously have a very detrimental effect on

battery life, as well as potentially present long term reli-

ability problems associated with the excess current flow.

FORCING INTERNAL RESET VIA

SOFTWARE

In all designs it is recommended that a software reset

sequence be sent to the EEPROM as part of the micro-

controllers power up sequence. This sequence guaran-

tees that the EEPROM is in a correct and known state.

Assuming that the EEPROM has powered up into an

incorrect state (or that a reset occurred at the microcon-

troller during communication), the following sequence

(which is further explained below) should be sent in

order to guarantee that the serial EEPROM device is

properly reset:

7 START Bit

7 Clock in nine bits of `1'

7 START Bit

7 STOP Bit

The first START bit will cause the device to reset from

a state in which it is expecting to receive data from the

microcontroller. In this mode the device is monitoring

the data bus in receive mode and can detect the

START bit which forces an internal reset.

The nine bits of `1' are used to force a reset of those

devices that could not be reset by the previous START

bit.This occurs only if the device is in a mode where it is

either driving an acknowledge on the bus (low), or is in

an output mode and is driving a data bit of `0' out on the

bus. In both of these cases the previous START bit

(defined as SDA going low while SCL is high) could not

be generated due to the device holding the bus low. By

sending nine bits of`1'it is guaranteed that the device will

see a NACK (microcontroller does not drive the bus low

to acknowledge data sent by EEPROM) which also

forces an internal reset.

The second START bit is sent to guard against the rare

possibility of an erroneous write that could occur if the

microcontroller was reset while sending a write com-

mand to the EEPROM, and, the EEPROM was driving

an ACK on the bus when the first START bit was sent. In

this special case if this second START bit was not sent,

and instead the STOP bit was sent, the device could ini-

tiate a write cycle. This potential for an erroneous write

occurs only in the event of the microcontroller being

reset while sending a write command to the EEPROM.

The final STOP bit terminates bus activity and puts the

EEPROM in standby mode.

This sequence does not effect any other I2C devices

which may be on the bus as they will simply disregard

it as an invalid command.

SUMMARY

This application note has presented ideas that are fun-

damental in nature, yet not always obvious, to the utili-

zation of I2C serial EEPROM devices. Ideally the

hardware/software engineer(s) takes these ideas into

consideration during system development and design

accordingly. It is recommended that the software reset

sequence detailed in this application note be added to

the system initilization code of any system that utilizes

an I2C serial EEPROM device.

REFERENCES

`I2C-Bus Specification', Philips Semiconductors, January

1992

`The I2C-Bus and How to Use It', Philips Semiconductors,

April 1995

) 1999 Microchip Technology Inc. DS00709B-page 3

AN709

NOTES:

2002 Microchip Technology Inc.

Information contained in this publication regarding device

applications and the like is intended through suggestion only

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

No representation or warranty is given and no liability is

assumed by Microchip Technology Incorporated with respect

to the accuracy or use of such information, or infringement of

patents or other intellectual property rights arising from such

use or otherwise. Use of Microchip's products as critical com-

ponents in life support systems is not authorized except with

express written approval by Microchip. No licenses are con-

veyed, implicitly or otherwise, under any intellectual property

rights.

Trademarks

The Microchip name and logo, the Microchip logo, FilterLab,

KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,

PICSTART, PRO MATE, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip Tech-

nology Incorporated in the U.S.A. and other countries.

dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, microPort,

Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,

MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode

and Total Endurance are trademarks of Microchip Technology

Incorporated in the U.S.A.

Serialized Quick Turn Programming (SQTP) is a service mark

of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

) 2002, Microchip Technology Incorporated, Printed in the

U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and Tempe, Arizona in July 1999. The

Company's quality system processes and

procedures are QS-9000 compliant for its

PICmicro. 8-bit MCUs, KEELOQ. code hopping

devices, Serial EEPROMs and microperipheral

products. In addition, Microchip's quality

system for the design and manufacture of

development systems is ISO 9001 certified.

Note the following details of the code protection feature on PICmicro.

MCUs.

7 The PICmicro family meets the specifications contained in the Microchip Data Sheet.

7 Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,

when used in the intended manner and under normal conditions.

7 There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-

edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.

The person doing so may be engaged in theft of intellectual property.

7 Microchip is willing to work with the customer who is concerned about the integrity of their code.

7 Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as "unbreakable".

7 Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of

our product.

If you have any further questions about this matter, please contact the local sales office nearest to you.

2002 Microchip Technology Inc.

M

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