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Odd number divide by counters with 50% outputs, synchronous clocks

Posted: 20 Jun 2005     Print Version  Bookmark and Share

Keywords:differential clock  duty cycle  synchronous 

The application note by ON Semiconductor offers new ideas and ways for using some devices in new applications. It specifically discusses techniques for designing odd number counters with synchronous clocks and 50 per cent outputs.

The first technique requires a differential clock that has a 50 per cent duty cycle, an extra flip flop, and a gate to allow odd integers, such as 3, 5, 7, 9, to have 50 per cent duty cycle outputs and a synchronous clock. The frequency of operations is limited by Tpd of the driving FF, Setup, and Hold of the extra FF, and the times cannot exceed one half on the incoming clock cycle time.

The design begins with producing a odd number counter (Divide By 3 for this discussion) by any means one wishes and add a flip flop, and a couple of gates to produce the desired function. Karnaugh maps usually produce counters that are lockup immune.

View the PDF document for more information.

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