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Implementing synchronous rectifiers in isolated topologies

Posted: 16 Apr 2002     Print Version  Bookmark and Share

Keywords:power 

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Implementing synchronous rectifiers

in isolated topologies

able on the secondary side in a

simple, effective and cheap

way. However, this information

canbederivedonthesecondary

side from the output of the iso-

lation transformer. Due to the

parasitic elements of the cir-

cuit, the synchronizing signal

withdrawn at the output of the

isolationtransformerisdelayed

with respect to the primary

PWM signal and may present

some oscillations especially in

discontinuous conduction

mode.

Therefore, the control tech-

nique meant to provide syn-

chronous rectifiers driving has

to be able to prevent even-

tualrisingofwrongopera-

tiveconditions,derivedby

any timing effect on the

synchronizationofthesig-

nal available on the sec-

ondary (PWM synchroni-

zationsignal)withrespect

to the primary PWM sig-

nal.

Using the output of the

isolation transformer as

thePWMsynchronization

signal, a very simple way

to make MOSFETs oper-

ate as rectifiers in isolated

topologies is the tech-

nique called "self-driven

synchronous rectifica-

tion."

Unfortunately, this tech-

nique experiences a very seri-

ous inconvenience. For in-

stance, in a forward converter,

the driving signal is dependent

by the way in which the main

transformer is demagnetized

(magnetic reset). Conse-

quently, the time in which the

body diodes of the free-wheel-

ing MOSFET is forced to con-

duct can be very long because

the driving signal for the gate is

missing. This affects the main

benefitsintroducedbysynchro-

nous rectification, restricting

the use of this method for driv-

ing synchronous rectifiers only

in combination with some par-

ticular, and proprietary mag-

netic reset techniques.

Inaddition,thistechniqueis

hard to implement when the

primary input voltage has a

verywiderangeofvariation,for

the difficulty of always having

toprovideavalueofdrivingsig-

nal compatible with the gates

ranges.

Therefore, in isolated to-

pologies with primary side con-

trol, the most suitable ap-

proach to drive synchronous

rectifiers requires a control cir-

cuit able to handle the synchro-

nization signal (clock) with-

drawn from the secondary of

theisolationtransformerandto

solveanyotherproblemregard-

ing the timing of the driving

signals for the two MOSFETs

with respect to the clock input.

In Figure1 the general clock

In isolated topologies, if the

mainPWMcontrollerislocated

on the secondary side, the task

of driving synchronous rectifi-

ers can be easily solved. In fact,

with the PWM signal available

on the secondary side it can be

usedtogeneratethedrivingsig-

nal for Synchronous Rectifiers,

by adding proper delays to each

transition to compensate the

propagation delays, which are

suffered by the driving signal

transferred to the primary side

through some coupling device.

The secondary side control

configuration, however, shows

several system disadvantages,

such as the requirement of an

auxiliary power supply to start

the converter, requirement of a

crossing-isolation circuit able

to transfer the PWM control

driving signal to the primary

switches and difficulties in

transferring the information

about the primary switch cur-

rent to the PWM controller, in

current mode control loops.

Therefore,theuseofPWMcon-

trol on the primary side is man-

datory to realize SMPS with top

performances in terms of high

efficiency, small dimensions

and low cost.

IfthemainPWMcontrolcir-

cuit is on the primary side, its

output signal cannot be avail-

signal at fixed switching fre-

quency, with primary switch on

and off time intervals is dis-

played. In Figure 2 the general

schematic of control driven

implementation in a forward

converter is shown.

Cross-conduction and

shoot-through problems

Whereitisnecessarytousesyn-

chronous rectifiers in isolated

topologies in a simple way, this

control circuit deals with the

propertiminggenerationofthe

Synchronous Rectifiers driving

signal from the clock signal in-

put. According to Figure1, and

as already explained, proper

deadtimesbetweenclocksignal

and SR driving signal must be

provided to avoid cross conduc-

tion between switches.

Another well-known phe-

nomenontobedealtwithbythe

controller is the so-called shoot

through problem that may hap-

pen on the secondary side of an

isolated topology. The specific

mechanism of this wrong op-

eration condition depends on

thecircuittopology.Ingeneral,

while the transition in which a

synchronous rectifier has to be

turned on is easy to deal with,

the turn-off transition requires

a special treatment. In fact, the

circuitry that generates the

driving signal from the clock

introducesapropagationdelay,

which is added to the one com-

ing from the isolation trans-

former.

Figure 1: Driving signals of synchronous rectifiers.

Figure 2: A control driven synchronous rectification in a forward converter.

Theseintrinsicdelaysgener-

ate late turn-off of the bi-direc-

tional synchronous rectifiers

switches, creating wrong cir-

cuit conditions, normally im-

possible for the presence of the

unidirectional diodes. The gen-

eralconditioncanbe defined as

the creation of short circuit

loops, which can generate very

high current peaks, limited

only by the parasitic elements

in the circuit. In Figure 3 this

shortcircuitconditionisshown

in the case of a forward topol-

ogy.

Therefore, the introduction

of a special dead time, able to

avoid the generation of the

wrong operation conditions, is

necessary. This can be realized

by generating a proper antici-

pation of the turn-off transi-

tion, able to guarantee that the

SRisturnedoffbeforetheclock

signaltransition. This anticipa-

tion, as in the turn-on transi-

tion, however, has to be mini-

mized to reduce the body-diode

conduction time, hence to

avoid penalties on the effi-

ciency. In particular the

amount of anticipation can be

used as an optimization param-

eter to adjust the operation of

the circuit to its physical imple-

mentation.

In fact, the time slope of the

decreasing current on the SR

that has been turned off de-

pends on several parameters,

such as input and output volt-

age of the converter, the

amount of previously driven

currentand,aboveall,thepara-

sitic elements in the circuit like

the leakage inductance. The

anticipation time can be

adapted to the specific opera-

tion condition of the circuit to

achieve the best performance

in terms of efficiency,

minimumizing the conduction

times of the body-diodes and

the consequent reverse recov-

ery currents.

In Figure 1 the required an-

ticipation intervals, denomi-

nated T1 and T2, are introduced

in the most general case of two

complementary outputs gener-

ated from a clock input.

Description of the new method

Thepresentedmethodismeant

to generate the proper driving

signals for synchronous rectifi-

ers from a clock signal input,

related to the main PWM signal

of the switch-mode circuit.

In particular, it is able to op-

erate according to the timing

displayed in Figure 2, realizing

proper anticipation times in

correspondence of the turning-

off transitions of the outputs.

These functions are imple-

mented through the basic con-

cept of synchronizing the op-

eration of the control circuit to

theclocksignalattheconverter

switchingfrequency,andinpar-

ticular to its transitions. This is

realized by means of an oscilla-

tor at a frequency much higher

than the switching frequency of

the converter and of the two

digital counter blocks that play

differentroles:oneoperatesthe

measure of the entire switching

period, cycle-by-cycle, storing

this information for the next

cycle. The other one makes the

samerevelationfortheonoroff

timeoftheclocksignal,accord-

ing to the specific need of the

circuit topology.

The precision and resolu-

tion of the system is related to

theinternaldigitalfrequencyof

operation, used to implement

this method. With the period

andon/offtimeintervalparam-

etersofthepreviouscyclebeing

available,apropertimingofthe

outputs can be easily generated

in the following cycle, and in

particularaproperanticipation

on the turning-off transitions

can be set. The amount of the

anticipation can be set accord-

ingly with the resolution of the

system, in terms of discrete

quantities of minimum digital

pulse period. The general ar-

chitecture of this system is

shown in Figure 4.

Timing of the proposed con-

trol technique will be shown in

the following figure, together

withthedetailedexplanationof

the control method operation,

according to the description of

the apparatus through which it

is implemented.

An internal oscillator, a fi-

nite states machine, two couple

of UP/DOWN Counters and

two control output logic blocks

(Figure 4) compose the general

structure of the system in the

more general case of two

complementary signals on the

secondary side (forward topol-

ogy). This structure has three

inputsandtwooutputs:theout-

puts are the driving signals for

the two MOSFETs on the sec-

ondary side of the converter;

the inputs are the clock, the

anticipationtimesettingforthe

OUT1 andtheanticipationtime

setting for the OUT2.

The finite states machine,

synchronized with the rising

edges of the internal oscillator

clock signal (CK1) at frequency

f1>fs (period T1) is the brain of

the system and generates the

two signals, OUT1 and OUT2,

without any overlap in turn-on

and turn-off conditions. A

square wave signal of fre-

quency fs (period Ts), called

switching frequency, is present

at the clock input; the anticipa-

tion times are externally set

through the relative inputs.

The two counters work in a dif-

ferent way, as DOWN works to

anticipate the turn-off of the

outputs and UP works to con-

tinuously get the information

about the duration of the

switching period for the OUT2

or about the duration of the

TON time for OUT1. In this way,

in a switching period, the an-

Figure 3: Shoot-through conditions in a forward converter.

Figure 4: General structure of the system.

ticipation in turn-off the out-

puts is based on the informa-

tion stored in the previous

switching period. Continuous

monitoring of the switching

period and of the TON time is

obtained cycle after cycle. The

number of bit of the counters

relative to the OUT2 are cho-

sen according to the minimum

and the maximum operating

switching frequency of the

converter. The numbers of bit

of the counters relative to the

OUT1 are chosen according to

the minimum and the maxi-

mum TON of the converter.

In steady state conditions

(fixed switching frequency and

fixed duty-cycle), for the two

following switching periods,

the part of the system relative

to the OUT2 operates as follows

(Figure 5):

First switching period: On the

rising edge of the clock input,

the first of the two UP/DOWN

counters starts to count as UP

the pulses of the internal clock

(CK1

). On the next rising edge

of the clock input (end of the

firstperiodTs

)thecounterstops

its calculation. The number of

pulses counted (n2

) reports the

duration of the switching pe-

riod. This information is stored

in order to be used in the next

switching period.

Secondswitchingperiod:Onthe

rising edge of the CK input, the

first counter counts as DOWN

the pulses of the internal clock

stoppingitscalculationton2-x2,

at this time OUT2 is turned off.

The second counter, counting

the new number of pulses of the

internal clock, updates the in-

formationonthedurationofthe

switching period Ts.

The amount of anticipation

inturning-offtheOUT2 isgiven

by x2 x T1, and is set by Antici-

pation2 input. In each

period the function of

the counters, UP or

DOWN, is exchanged

withrespecttothepre-

vious period.

For the part of the

system relative to the

OUT1 other two UP/

DOWN counters take

in account the infor-

mation on the dura-

tion of the TON time in

order to anticipate the

turn-off of the OUT1

(Figure 6):

First switching period:

Thefirstcounterstarts

to count on the rising

edge of the clock input

and stops its calcula-

tion on the falling

edge. The number of pulses

counted is n1 and this informa-

tion gives the TON time.

Second switching period: The

first counter counts as DOWN

stopsitscalculationton1-x1 giv-

ing anticipation in turning-off

the OUT1 equal to x1 x T1, this

anticipation is set through the

OUT1 Anticipation1 input. The

second counter counts upward

the number of pulses of the in-

ternal clock between the rising

edge and the falling edge of the

clock input during the current

period.

When the Clock input is

variable in terms of TON time

and switching period, it is pos-

sible to have different condi-

tions between a first switching

period and the following sec-

ond switching period. All these

conditions can bring wrong

calculations.

The source of these variable

conditions is, in any case, the

PWM controller of the con-

verter.Forexample,inaswitch-

ingconverter,ifaloadvariation

occurs, the PWM controller

will increase or decrease the

TON time in order to keep the

regulation of the output volt-

age. The speed of this TON time

variation is dependent on the

control loop bandwidth

of the converter. In gen-

eral the maximum allow-

able control loop band-

width of a switching con-

verter is one tenth of the

switching frequency.

This means that this

method, acting on the

next cycle after a varia-

tion occurs, is fast

enough to manage these

variableconditionswith-

out any problem.

This method of con-

trolling the turn-off

time of Synchronous

Rectifiers is actually in

course of implementa-

tion in the design of a

silicon device family

(STSRx). These devices,

each one designed for a

specific topology appli-

cation, forward, flyback

and double ended to-

pologies, together with other

functions not object of this ar-

ticle, will allow the implemen-

tation of synchronous rectifi-

cation technique in isolated to-

pologies in an economical and

easy way.

By Fabrizio Librizzi

Application Engineer

Voltage Regulator BU

Discrete & Standard ICs Group

STMicroelectronics

E-mail: fabrizio.librizzi@st.com

Figure 6: OUT1 anticipation time generation.

Figure 5: OUT2 anticipation time generation.





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