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Odd number divide by counters with 50 percent outputs and synchronous clocks

Posted: 11 Dec 2000     Print Version  Bookmark and Share

Keywords:Odd number divide 

Counters With 50% Outputs and Synchronous Clocks Prepared by: Cleon Petty and Paul Shockman Product Applications ON Semiconductor The application inquiries handled by the Product Applications gives opportunities to solve customer needs with new ideas and learn of ways the customer has used our devices in new applications. A couple of these calls lead to techniques of designing odd number counters with synchronous clocks and 50% outputs.

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) Semiconductor Components Industries, LLC, 1999 October, 1999 - Rev. 0 1 Publication Order Number: AND8001/D AND8001/D Odd Number Divide By Counters With 50% Outputs and Synchronous Clocks Prepared by: Cleon Petty and Paul Shockman Product Applications ON Semiconductor The application inquiries handled by the Product Applications gives opportunities to solve customer needs with new ideas and learn of ways the customer has used our devices in new applications. A couple of these calls lead to techniques of designing odd number counters with synchronous clocks and 50% outputs. The first technique requires a differential clock, that has a 50% duty cycle, a extra Flip Flop, and a gate to allow Odd integers, such as 3, 5, 7, 9, to have 50% duty cycle outputs and a synchronous clock. The frequency of operations is limitedbyTpdofthedrivingFF,Setup,andHoldoftheextra FF, and the times cannot exceed one half on the incoming clock cycle time. The design begins with producing a odd number counter (Divide By 3 for this discussion) by any means one wishes and add a flip flop, and a couple of gates to produce the desired function. Karnaugh maps usually produce counters that are lockup immune. Example: Specify, Divide By 3, 50% duty cycle on the output Synchronous clocking 50% duty cycle clock in Using D type Flop flips and karnaugh maps we find; Ad = A*B* and Bd = A (Note: * indicates BAR function) Figure 1 shows schematic and timing of such a design. Figure 1. Q QD C Q QD C Divide By 3 A B APPLICATION NOTE AND8001/D 2 Using the technique, we add a gate on the clock to get differential Clock and Clock bar, a flip flop that triggers on the Clock Bar rising edge (Clock Neg.) to shift the output of "B" by 90 degrees and a gate to AND/OR two FF output to produce the 50% output. We get Figure 2, a Divide By 3 that clocks synchronously with 50% output duty cycle. Figure 2. Q QD C Q QD C Divide By 3 W/50% out Q QD C 50% Out Clk in A B C Clk AQ BQ CQ OUT The Max frequency of the configuration (figure 2) is calculated as Clock input freq./2 = Tpd of FF "B" + Setup of "C" + Hold of "C". Example: Tpd = 1Ns, Setup = !NS and Hold time = 0Ns. with these numbers the Max Frequency the configuration can expect is; Cycle time = 2*(1 + 1)Ns or 4 Ns that converts to 250MHZ. The Method is usable on other divide by "N" counters as well by using the same methodology. The use of different types of Flip Flops (J,K, S,R, Toggle, ETC.) may produce fewer components. The type logic used may also dictate configuration. The configuration should always be checked for lockup conditions before the design is committed to a production. Example: ADivideBy3designhasallpossiblestatesshowninchart 1 but uses only the states shown in chart 2 leaving the states 2,3,4,5, & 7 for possible lockup. A B C 0 0 0 0 1 1 0 0 2 0 1 0 3 1 1 0 4 0 0 1 5 1 0 1 6 0 1 1 7 1 1 1 Chart 1 Chart 2 A B C 0 0 0 0 1 1 0 0 6 0 1 1 AND8001/D 3 We need to know that the counter will go into the flow, shown in chart 2, if it happens to come up in one of the unused states at powerup or for any other reason. Figure 3 shows the resulting flow chart of the analysis of the Divide By 3 counter of Figure 2. There is no state that the counter can begin in that doesn't lead to the desired flow after one clock cycle. Figure 3. 011 111 100 001 000 010 110 101 Observation shows that FF "C" follows FF "B" by a half a clock cycle and will never be able to lockup making the analysis of the Divide By 3 sufficient to assure the whole configurationwill have no lockup flow. So; only the 1 1 state of the divide by three needed to be confirmed. Themethodisextendibletootheroddlargerdivideby"N" numbers by following the same design flow. a) Design a stable UP or Down divide by "N" counter b) Make the Clock input a 50% duty cycle differential signal c) Add a FF to follow one of the FF's in the counter by 1/2 clock cycle d) OR/AND the shifted FF with the one that is driving it to obtain the desired 50% output Example: Design a 50% Divide By 9 Use "D" type FF's, other types may give smaller component count Karnaugh maps yield: Ad = A*B* Bd = A*B + AB* Cd = ABC* + CB* + A*C Dd = ABC AND8001/D 4 Figure 4. Q QD C Divide By 9 50% Counter Q QD C 50% Out Clk A E Q QD C B Q QD C C Q QD C D C C Clk AQ BQ CQ OUT DQ EQ Choosing to use "C" as the flip flop to delay by a 1/2 clock cycle is necessary to accomplish the 50% output required when "ANDed" with "E". Another Synchronous 50% counter for Divide By 6, 10, 12, 14, 18, etc. can be realized by the additions of a J K FF and some gates. Other types of FF's may be used. AND8001/D 5 Take the before mentioned Divide By 3 add a J K and a divideby6,50%dutycycle,synchronouscounterisrealized as shown in Figure 5. Figure 5. Q QD C Q QD C Clk Q QJ C K 50% Out Divide By 6 50% Out Clk AQ BQ OUT, CQ A B C Of course, there are better ways to realize a Divide By 6 but it does demonstrate how the method works. Note this configuration does not require a 50% input clock duty cycle and it is synchronous. This type of configuration could be useful in a clock generating PLL chip where a Divide By 3 and Divide By 6 are needed to synchronize two signals as shown in figure 6. AND8001/D 6 Figure 6. Q QD C Q QD C Q QD C Divide By 3 50% Out Clk in A B C Q QJ C E K Divide By 6 50% Out D CLK AQ BQ CQ DQ OUT, EQ Notice FF "A" was chosen as the FF to drive FF "E" in order to align the positive edges of the clock, Divide By 3, and divide by 6. The overall skew of the output could be better matched if all the same type of FF and gates are used. We already know the Divide By 3 is lockup immune, following flow chart Figure 7 shows that the addition of the J K does not change that situation for the Divide By 6. Figure 7. Divide by 6 Flow Chart 011 101 100 010 000 001 111 110 The flow shows no lockup, but if one observes that the J K is a sort of toggle device it is obvious that it can't lock up the counter. The J K may need bigger input AND gates to accomplish larger divide numbers. As an example, pick a Divide By 12 and use J K type FF's to do the function. AND8001/D 7 Maps show: Ja = 1 JB = AC* Jc = AB Ka = 1 Kb = A Kc = A Figure 8 shows the implementation. Figure 8. Synchronous Divide By 12 CLK AQ BQ CQ OUT, DQ Q Q J C Q QJ C Clk Q QJ C K 50% Out Ja = 1 Jb = AC Jc = AB Jd = ACD Ka = 1 Kb = A Kc = A Kd = ACD K KQ Q J C K H A B C D A B C D 0 0 0 0 0 1 1 0 0 0 2 0 1 0 0 3 1 1 0 0 4 0 0 1 0 5 1 0 1 0* 6 0 0 0 1 7 1 0 0 1 8 0 1 0 1 9 1 1 0 1 10 0 0 1 1 11 1 0 1 1* The truth table shows that the FF "D" must change state at 5 and 13 Examination of the truth table shows that the FF "D" must decodea5anda13inordertomakethedesire50%function. The inputs to the "D" FF are J = ACD* and K = ACD and requires 3 input AND gates. For larger counters the inputs on the AND gates will need to increase to reach the desired configuration; However for the single digit integers such as 3, 5, 7, & 9 to realize 6, 10, 14, & 18 a fan in of three is max. The methods are expandable. A little observation, thinking, and logic typing will allow the designer to minimize the component count and skew on this type of counter. AND8001/D 8 USA/EUROPE Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: [email protected] Fax Response Line*: 303-675-2167 800-344-3810 Toll Free USA/Canada *To receive a Fax of our publications N. America Technical Support: 800-282-9855 Toll Free USA/Canada ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes withoutfurther notice to any products herein. SCILLC makes no warranty,representationorguaranteeregardingthesuitabilityofitsproductsforanyparticular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorneyfees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION ASIA/PACIFIC: LDC for ON Semiconductor - Asia Support Phone: 303-675-2121 (Tue-Fri 9:00am to 1:00pm, Hong Kong Time) Email: [email protected] JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-8549 Phone: 81-3-5487-8345 Email: [email protected] ON Semiconductor Website: For additional information, please contact your local Sales Representative. AND8001/D

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