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MediaTek adopts IC Compiler for 65nm SoC designs

Posted: 10 Jun 2008     Print Version  Bookmark and Share

Keywords:IC compiler  SoC designs  chip design 

Synopsys, Inc. today announced that MediaTek, Inc. has adopted Synopsys' IC Compiler for its next-generation 65nm SoC designs. IC Compiler was recently used to complete a hierarchical chip design that contained 4.5-million instances running at 700 megahertz (MHz). Additional stringent criteria included high-performance timing optimisation, low power, hierarchical design support and fastest time with highest quality of results (QoR).

"Our market environments are fast-moving and demanding, where time-to-market can be the difference between success and failure. Synopsys' IC Compiler demonstrated that it can meet the design requirements we need to deliver a high-quality product as quickly as possible. Our intent is to move towards a concurrent hierarchical design flow," said MediaTek.

MediaTek decided to do the design hierarchically to speed turnaround time. IC Compiler's hierarchical design takes a "divide and conquer" approach that allows several blocks to be implemented and optimised simultaneously instead of sequentially. This technique also allows engineering change orders (ECOs) to be applied much faster. At the top level, IC Compiler utilises smart hierarchical modelling technology, a technique that uses an abstract version of a block instead of a detailed block to expedite physical design while preserving interface circuitry so that optimisations can be applied across all blocks. This approach yields similar results as the fully-instantiated model- less flow, but has the advantage of a much faster turnaround time while achieving excellent correlation with the PrimeTime sign-off solution. In addition, MediaTek achieved high correlation between hierarchical models and flat models.

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