Global Sources
EE Times-India
EE Times-India > EDA/IP

Synopsys define 'first' low-power verification methodology

Posted: 05 Jun 2008     Print Version  Bookmark and Share

Keywords:low-power verification  low power designs  power management 

Synopsys Inc., has collaborated with ARM and Renesas Technology to define the industry's first methodology to address the rapidly increasing complexity of low power verification. The companies are documenting the methodology in a new book titled "Verification Methodology Manual for Low Power Designs" (VMM-LP) that will enable rapid and broad deployment of industry best practices for comprehensive verification of low power designs. The new VMM-LP is based on the collective verification and IP experience of ARM, Renesas, and Synopsys, and builds on the methodology originally published in the proven "Verification Methodology Manual for SystemVerilog" book developed by ARM and Synopsys.

The adoption of aggressive power management techniques has led to an increase in verification complexity, creating a need for a structured and reusable verification environment to achieve power goals and first-pass silicon success. The VMM-LP documents the common causes of low power bugs, provides rules and guidelines for low power verification, specifies a SystemVerilog base class library facilitating the setup of a reusable verification environment, and recommends assertions and coverage techniques to achieve comprehensive low power verification. The source code for the SystemVerilog base class library described in the VMM-LP book will be made available with VMM standard libraries and applications under the popular Apache 2.0 open source licence.

"In 2007, 2.9 billion ARM Powered processors were shipped into the market. As a leading provider of low-power semiconductor IP, we recognise the need for a rigorous verification methodology for successful deployment and integration of that IP," said John Goodenough, worldwide director of design technology for the office of the CTO at ARM. "The Verification Methodology Manual for Low-Power Design helps address this need by capturing the collective expertise and methodologies of industry low-power leaders across multiple market segments."

"Comprehensive functional verification of our aggressively power-managed SoCs—especially PMP-targeted devices containing tens of power states—is a major engineering challenge. We believe the VMM-LP book will be a powerful tool in the hands of the chip verification community in achieving predictable verification closure of LP designs," said Santhosh Madathil, VLSI design and verification practice group head at Wipro Technologies.

Low-power design techniques are used across electronic product market segments ranging from handhelds to enterprise servers. In addition to voltage-aware static and dynamic verification tools, such as MVSIM with VCS and MVRC, which are part of the Eclypse low power solution from Synopsys, designers require a rigorous methodology to set up testbenches, generate test cases, attain coverage closure and pinpoint bugs using assertions. The VMM-LP methodology addresses these needs with guidelines, rules, assertions, coverage, and base classes based on proven industry best practices.

"Our goal is to achieve first-pass silicon success for all of our power-managed designs," said Narayana L. Pidugu, senior director of the Hyderabad design centre at Cypress Semiconductor. "Given our highly compressed development cycle, there is immense pressure on functional verification schedules. The methodology described in the VMM-LP is easily implemented by the MVSIM and MVRC low-power verification tools, which have already helped achieve our product development goals by enabling us to successfully deploy sophisticated power-management verification techniques in a consistent and reusable manner."

"Low-power design techniques add an extra verification dimension to getting the product right the first time," said Hitoshi Sugihara, department manager of the DFM and digital EDA technology development department at Renesas. "We have successfully implemented the verification methodology for low power described in the VMM-LP book through our use of Synopsys' products. The VMM-LP methodology systematically outlines the best practices for low-power verification and will serve as a basic verification reference guide for Renesas."

"Tools alone are not enough to address the verification challenges of multi-voltage techniques used in low-power designs," said Manoj Gandhi, senior VP and general manager of the verification group at Synopsys. "Lack of a verification methodology for low power has created a significant void. We have collaborated with some of the low-power leaders in the industry by combining the verification expertise at ARM and Renesas to define a leading-edge, reusable methodology."

Comment on "Synopsys define 'first' low-power ve..."
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top