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Intel-Micron duo rolls 34nm NAND device

Posted: 02 Jun 2008     Print Version  Bookmark and Share

Keywords:NAND  multi-level cell  monolithic 

IM Flash Technologies LLC, a joint NAND venture between Intel and Micron developed the industry's 'first' sub-40nm NAND flash device. The Intel-Micron duo has been able to introduce this by rolling out 34nm, 32Gbit multi-level cell (MLC) chip. Previously, the leading-edge NAND device from Intel and Micron was a 50nm part.

This process technology was jointly developed by IM Flash Technologies LLC, a joint NAND venture between Intel and Micron.

A single 32Gbit chip could store more than 2,000 digital photos or hold up to 1,000 songs on an MP3 player, according to the companies. The 32Gbit NAND chip is said to be the only monolithic device at this density that fits into a standard 48-lead TSOP, said Brian Shirley, vice president of Micron's Memory Group.

''These advancements will expand the value proposition and accelerate the adoption of solid-state drive (SSD) solutions in computing platforms,'' said Pete Hazen, director of marketing of Intel's NAND Products Group, in a statement.

The device will enable more cost-effective SSDs, doubling the current storage volume of these devices and driving capacities to beyond 256GB in today's standard, smaller 1.8-inch form factor.

Two 8-die stacked packages would realise 64GB of storage. This is enough for recording anywhere from eight to 40 hours of high-definition video in a digital camcorder, according to Micron and Intel.

The 34nm 32Gbit chips will be manufactured on 300mm wafers. The device measures just 172mm². Shipments of samples begin in June and mass production is expected during the second half of this calendar year.

Based on the 34nm architecture, Intel and Micron also plan to introduce lower-density MLC products. Single-level cell products (SLC) are due out by the end of this year.

Analysts were impressed. Intel and Micron have basically leapfrogged the competition, said Gregory Wong, an analyst with Forward Insights Co. The main competition includes Hynix, Samsung and Toshiba/SanDisk.

How to make 34nm NAND flash?
''Owing to the aggressive gate half-pitch, immersion lithography with self-aligned double patterning employing spacers is most likely being used'' by IM Flash to produce the latest part, Wong said in an e-mail regarding the part. ''Also expect changes in the bitline and wordline materials as well as a higher k interpoly dielectric in comparison to the 50nm generation.''

Other vendors are not far behind. ''If the ramp of IMFT's 50nm 16Gbits device is any guide, we should expect to see volume in December or in Q1/09,'' Wong said.

''It's quite remarkable that Intel-Micron have managed to catch up and surpass the other NAND flash vendors in the short span of three years,'' he added. ''IM Flash achieved this milestone by skipping the 6xnm and 4xnm nodes. However, any cost advantage could be short-lived if IM Flash fails to ramp up the technology smoothly and SanDisk/Toshiba ramps its 43nm 32Gbit x3 in Q1/09 as planned.''

At present, the Toshiba/SanDisk duo are shipping 43nm NAND devices. The companies are looking to ship a three-bit-per-cell technology.

The minimum feature size of Samsung's latest 16Gbit MLC NAND flash is 51nm, said Young Choi, memory technology manager at Semiconductor Insights, a TechInsights company specialising in in-depth technical investigation of ICs and electronic systems.

- Mark LaPedus
EE Times

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