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Design library target FPGA synthesis

Posted: 29 May 2008     Print Version  Bookmark and Share

Keywords:FPGA  RTL  foundation library 

EVE has announced the availability of DW-FPGA, a DesignWare foundation library for use with FPGA synthesis software.

DW-FPGA offers register transfer level (RTL) source code for the most commonly used DesignWare Foundation Library intellectual property (IP) components from Synopsys Inc. DW-FPGA supports XST from Xilinx, Quartus from Altera, Synplicity's SynplifyPro and Precision from Mentor Graphics Corporation, along with languages Verilog, VHDL and SystemVerilog. It can be used with or without EVE's ZeBu and for simulation, emulation, prototyping and FPGA designs.

When implementing an application specific integrated circuit (ASIC) design on an FPGA or an FPGA prototyping board, the original ASIC design often uses DesignWare Foundation components not readily available for an FPGA implementation. With DW-FPGA, whenever ASIC-based RTL code references a DesignWare component of the foundation library, the synthesis tool automatically uses the synthesisable definition contained in the provided source code to infer an optimised FPGA description. DW-FPGA includes typical DesignWare functions, including adders, subtracters, multipliers, dividers, cosines, and squareroot.

DW-FPGA will be demonstrated, along with EVE's entire line of hardware/software co-verification solutions, during the 45th Design Automation Conference (DAC) on June 9-12 at the Anaheim Convention Centre in Anaheim, California.

- Clive Maxfield
Programmable Logic DesignLine

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