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Software enhances FPGA performance

Posted: 21 May 2008     Print Version  Bookmark and Share

Keywords:FPGA  real-time  multi-processor  compile times 

Altera Corp. has released version 8.0 of its Quartus II software and claims that it can deliver, on average, a full two-speed grade advantage and 3X faster compile times for high-end FPGAs.

"Our customers continue to emphasize the importance of FPGA design productivity in the race to get products to market," said Chris Balough, marketing director for software, embedded, and DSP at Altera.

Users of the 8.0 version on Windows platforms will notice compile times reduced by up to 50 per cent, with an average reduction of 22 per cent, according to the company. Designs leveraging multi-processor-based servers will obtain an even higher compile time advantage using the FPGA design software with multi-processor support.

Quartus II software's incremental compilation feature is aimed to offer users a second-to-none productivity advantage, capable of delivering up to a 70 per cent compile time reduction compared to a standard compilation. During the process of creating incremental compilation design partitions, an interactive graphical user interface (GUI) provides real-time feedback, such as logic resource usage and inter-partition timing paths, enabling designers to explore and quickly determine the most effective partition scheme.

Quartus II software also includes additional enhancements such as new tasks window, enhanced FPGA I/O planning, new IP advisor, SOPC builder, MegaCore IP Library, new floating point, and delay lock loop and memory initialization megafunctions.

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