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EE Times-India > EDA/IP

Software speeds up RTL power reduction

Posted: 20 May 2008     Print Version  Bookmark and Share

Keywords:RTL  power reduction  clock  memory  datapath 

Sequence Design has introduced PowerArtist, claimed to offer the industry's fastest automated RTL power reduction-10 to 50 percent or more depending on the design-in just minutes on a million-plus gate block. The product is said to have run on a 15M gate design in four hours within a 12GB footprint.

Built upon the foundation of Sequence RTL DFP (Design For Power) power analysis technology, PowerArtist focuses on trimming power in three key areas: clock, memory, and datapath at RTL where designers have maximum opportunities for power reduction-over and above those achieved during synthesis.

PowerArtist integrates with all standard design flows, including synthesis and formal verification. It allows users to automate proprietary power reductions using the Si2 OpenAccess database with its open API.

Flow 1: During new RTL design, use PowerArtist before simulation. Flow 2: For legacy RTL, use PowerArtist with formal verification.

"Great artists require two things to create their masterpiece: inspiration and superior equipment. With PowerArtist, designers will now have an RTL power-reduction tool worthy of their skills," said Sequence president and CEO, Vic Kulkarni.

Features and benefits

PowerArtist is claimed to significantly increase productivity by offering the flexibility to either pinpoint and manually edit RTL, or reduce power automatically with multiple techniques. Clock power, for instance, can make up 60 per cent of SoC power consumption, but PowerArtist automatically reduces clock power and generates constraints to drive synthesis for power-smart and additional clock gating. Unlike synthesis, PowerArtist can quickly analyze the registers lacking enables for which it either finds or creates enable signals. It also analyzes signal activity over time to determine the power-efficiency of enables and identify the registers for synthesis to clock gate.

It likewise reduces memory power at RTL by gating memory clocks, memory splitting and uncovering extraneous memory activity. During early customer testing, PowerArtist realized 60 percent total power savings based on memory techniques alone for a networking design application. PowerArtist also reduces power by identifying wasted datapath activity.

PowerCanvas Advanced GUI supports PowerArtist by providing an interactive environment to graphically pinpoint and understand power reductions while managing RTL changes. Users can sort and filter results, cross-probe to schematic logic cones downstream and upstream, and accept or reject RTL changes.

PowerArtist will begin shipping Q2, 2008. North America list pricing starts at Rs.88.05 lakh ($220,000) for a one-year TBL.

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