Global Sources
EE Times-India
Stay in touch with EE Times India
EE Times-India > T&M

How to provide a power-efficient architecture

Posted: 24 Jul 2006     Print Version  Bookmark and Share

Keywords:leakage power  transistors  multi-processing 

Moore's Law is alive and well and the ability to integrate more transistors onto a single device will continue to scale well into the future. However, as process technology advances, we face new challenges that require new techniques for control of active and leakage power. We can use more transistors to achieve higher performance at lower power, as in the case of special purpose hardware. Multi-processing will allow performance to scale while maintaining or reducing total power consumption and enable more efficient energy per instruction usage.

Some effects of semiconductor process technology advancements that could be ignored in previous process generations are having increasing impacts on transistor performance and ways to deal with those effects must be found.

View the PDF document for more information.

Comment on "How to provide a power-efficient arc..."
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top