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Accomplish manufacturing test at low power

Posted: 01 Feb 2008     Print Version  Bookmark and Share

Keywords:low-power manufacturing tests  peak power consumption  compression circuits 

Excessive peak power consumption during test adds delays that can lead to unpredictable test results, and thermal problems caused by excessive average power during test can damage devices. If not properly addressed, both can increase costs for manufacturers. Designers are now combining advances in test automation with DFT methods to create low-power manufacturing tests.

By understanding how low power fill works, it is easy to see why it�s necessary that each block have its own compression circuit. If the compression is "flat," then the decompressor�s outputs fan out to scan chains across all the blocks. The care bits of the block under test are then needlessly scanned into all the other blocks, contributing to a large number of logic state transitions. In contrast, inserting compression circuits inside the blocks limits the fanout to scan chains inside each block, essentially creating care bit �boundaries� that can�t be traversed during shift operations. Embedding the compression logic inside a design�s physical hierarchy has the further benefit of reducing wire routing congestion, which can contribute substantially to the area overhead cost of compression.

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