Global Sources
EE Times-India
Stay in touch with EE Times India
EE Times-India > Manufacturing/Packaging

Achieve low-power manufacturing test

Posted: 16 Jan 2008     Print Version  Bookmark and Share

Keywords:DFT methods  ATPG technology  low power manufacturing tests  digital circuit test 

Peak power and average power are two kinds of dynamic power consumption that affect device testing. Peak power can cause power rails to collapse. On the other hand, average power can cause thermal problems that can damage the device. So semiconductor and design automation industries focus on unobtrusive ways to reduce both peak power and average power.

Managing power consumption during test is important because the fabrication processes enable the manufacture of designs containing scan flops. Manufacturers are turning to ultra-high resolution at-speed testing to detect very small delay defects inside devices. The use of power-aware testing techniques now rely on advanced ATPG technologies to maintain high-test quality in the presence of nanometre defects.

View the PDF document for more information.

Comment on "Achieve low-power manufacturing test"
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top