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Top 10 methods for ASIC power minimization (2)

Posted: 10 Jan 2007     Print Version  Bookmark and Share

Keywords:submicron ASICs  power minimization  low power techniques  multiple-voltage supplies 

Since both dynamic power and leakage power scales with the square of the supply voltage, the operating voltage should be minimized at all times. Currently, there are three well-supported techniques for doing so: multiple-voltage supplies, variable-supply voltages, and supply shut-off switches.

By using multiple-supply domains on a single chip, non-speed critical blocks can run at low voltages and low frequencies, while critical processing blocks can run at high frequencies and high voltages without adversely affecting the power of the whole chip. If there was only one voltage domain, the voltage of the whole chip would have to be specified according to the voltage needed for the speed critical block.

This is the second part of a two part article focusing on power minimization in deep submicron ASICs. It discusses five effective implementation level low power techniques.

View the PDF document for more information.

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