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EE Times-India > EDA/IP

Total Power Optimization in RTL-to-GDSII Implementation Flow

Posted: 12 Mar 2007     Print Version  Bookmark and Share

Keywords:RTL-to-GDSII  low-power designs  low-power analysis 

Design power closure and circuit power integrity in large and complex digital integrated circuit designs have become one of the main drains on engineering resources, thereby impacting the device's total time-to-market.

Whenever the industry moves from one technology node to another, existing power constraints are tightened and new constraints emerge. Creating optimal low-power designs involves making tradeoffs at different stages of the design flow. Successful power-sensitive designs require engineers to have the ability to accurately and efficiently perform these tradeoffs. In order to achieve this, engineers require access to appropriate low-power analysis and optimization engines, which need to be integrated with ? and applied throughout ? the entire RTL-to-GDSII flow.

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