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Good behavioural model simulation: predicting first-order PLL synthesiser performance (Part I)

Posted: 10 Dec 2007     Print Version  Bookmark and Share

Keywords:PLL synthesizer  RFDE  ADS  simulation tools 

In this article, the phase noise of a closed-loop, phase-locked loop (PLL) synthesiser is simulated using an RF Design Environment (RFDE) and Advanced Design System (ADS) tools. The critical sub-circuits, such as the voltage-controlled oscillator (VCO), phase frequency detector (PFD) and charge pump (CP) are simulated separately and then modelled using behavioural models. The simulation results match the measured data of the IC to the first order.

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