Global Sources
EE Times-India
 
EE Times-India > EDA/IP
 
 
EDA/IP  

Good behavioural model simulation: predicting first-order PLL synthesiser performance (Part I)

Posted: 10 Dec 2007     Print Version  Bookmark and Share

Keywords:PLL synthesizer  RFDE  ADS  simulation tools 

In this article, the phase noise of a closed-loop, phase-locked loop (PLL) synthesiser is simulated using an RF Design Environment (RFDE) and Advanced Design System (ADS) tools. The critical sub-circuits, such as the voltage-controlled oscillator (VCO), phase frequency detector (PFD) and charge pump (CP) are simulated separately and then modelled using behavioural models. The simulation results match the measured data of the IC to the first order.

View the PDF document for more information.





Comment on "Good behavioural model simulation: p..."
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
 
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

 
Back to Top