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Simplifying PLL Design

Posted: 12 Feb 2008     Print Version  Bookmark and Share

Keywords:PLL design  RF design  behavioural modelling 

Phase lock loop (PLL) design poses a key challenge in RF design. Escalating noise limitations and increasingly aggressive performance requirements demand simulation strategies that allow designers to characterise performance to high levels of accuracy quickly so they can identify any architectural issues early in the development cycle. By leveraging the latest advances in behavioural modelling and RF tool design, engineers can now take advantage of near-transistor-level accuracy without incurring the long simulation runtimes traditionally associated with that approach.

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