Global Sources
EE Times-India
Stay in touch with EE Times India
 
EE Times-India > Interface
 
 
Interface  

Low Power Design For Analogue/Mixed-Signal IP

Posted: 04 Mar 2008     Print Version  Bookmark and Share

Keywords:analogue  mixed signal  IP  Link Power Management 

Power reduction and management techniques using multiple clock and power domains and power gating are effective for digital circuits. In analogue design, however, lowering power consumption must be considered early in the design phase. Starting with techniques for lowering the power consumption in analogue circuits, this article focusses on low power design for high speed serial interconnects. Different architectures for output drivers and methods for ac-coupled systems such as PCI Express, SATA, and XAUI is discussed. System designers influence the specifications of high speed serial interconnect; a good example of this is the emerging standards for the USB protocol—LPM and HSIC. USB is prevalent as the high speed serial interconnect in portable devices such as smart phones and mobile internet devices. Link Power Management (LPM) aims to reduce power consumption of USB devices and hosts, potentially extending battery life by at least 20 per cent. HSIC or "high speed inter-chip USB" allows low power high-speed data transfers (480 Mbps) using a source synchronous clocked serial interface. Both are reviewed in this article.

View the PDF document for more information.




Comment on "Low Power Design For Analogue/Mixed-..."
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
 
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

 
Back to Top