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Low Power Design For Analogue/Mixed-Signal IP

Posted: 04 Mar 2008     Print Version  Bookmark and Share

Keywords:analogue  mixed signal  IP  Link Power Management 

Power reduction and management techniques using multiple clock and power domains and power gating are effective for digital circuits. In analogue design, however, lowering power consumption must be considered early in the design phase. Starting with techniques for lowering the power consumption in analogue circuits, this article focusses on low power design for high speed serial interconnects. Different architectures for output drivers and methods for ac-coupled systems such as PCI Express, SATA, and XAUI is discussed. System designers influence the specifications of high speed serial interconnect; a good example of this is the emerging standards for the USB protocol—LPM and HSIC. USB is prevalent as the high speed serial interconnect in portable devices such as smart phones and mobile internet devices. Link Power Management (LPM) aims to reduce power consumption of USB devices and hosts, potentially extending battery life by at least 20 per cent. HSIC or "high speed inter-chip USB" allows low power high-speed data transfers (480 Mbps) using a source synchronous clocked serial interface. Both are reviewed in this article.

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