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Avail free Xilinx ref kit for SFI-5 designs

Posted: 07 Mar 2008     Print Version  Bookmark and Share

Keywords:hardware-verified  reference design  communication 

Xilinx Inc. has made available a free hardware-verified reference design and third party IP for the Optical Internetworking Forum (OIF) Serdes framer interface level 5 (SFI-5) standard. The SFI-5 interface enables communication between the optical transmission devices and the network processing system.

Based on 65nm Xilinx Virtex-5 LX330T FPGAs, the reference design accelerates the development of wired networking systems requiring 40Gbit/s payload rates, enabling applications using transport interfaces like OC768/STM256 and OTN OTU-3 in systems such as optical cross connects, fibre optics terminators and repeaters, 40G muxes, and test equipment.

The reference design has been hardware verified on the Xilinx ML525 evaluation platform and characterised for skew, temperature, process and voltage variations to ensure reliable interface, compatible with the OIF SFI-5 standard. Leveraging the industry's lowest power transceivers—typically, consuming less than 100mW per transmitter/receiver pair—this Virtex-5 LXT FPGA-based reference design uses 17 transceivers (16 for data and one for calibration).

"Networking equipment is rapidly moving to 40G payload rates where SFI-5 provides the chip-to-chip interface to the optical transponders," said Anil Telikepalli, senior manager of platform solutions marketing at Xilinx. "The Virtex-5 LXT FPGA platform is ideal for implementing the SFI-5 PHY, as well as additional logic blocks such as forward error correction and framer. The hardware-verified SFI-5 reference design takes advantage of the industry's only 65nm FPGA in production today with built-in low-power transceivers, providing generous deskew margin on the receiver side for sustained operation under changing system conditions."

Wired networking designers seeking additional Virtex-5 LXT FPGA solutions for 40G system design can also benefit from IP offerings from Xilinx Alliance program participant Avalon Microelectronics for 40Gbit/s applications, including: SxI-5-compliant SFI-5 physical layer core, 40G SONET-768/SDH-256 core with POS and 43G OTU-3 with G.709 FEC or other Enhanced FEC.

The free reference design for SFI-5 interface is available for download at the Website. The Virtex-5 LX330T FPGA is available today and the ML525 development board will be available in May.

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