Global Sources
EE Times-India
Stay in touch with EE Times India
EE Times-India > Manufacturing/Packaging

16Gbit NAND fabricated with 43nm tech debuts

Posted: 11 Feb 2008     Print Version  Bookmark and Share

Keywords:NAND  flash memory  CMOS 

Toshiba Corp. has developed a 16Gbit NAND flash memory chip fabricated with 43nm process co-developed with SanDisk Corp. The technology of the new chip was reported at last week's International Solid-State Circuits Conference.

The new 16Gbit products have a chip area of approximately 120mm², about 30 per cent less than the same-density NAND flash memories jointly developed by Toshiba and SanDisk and fabricated with 56nm process technology. Memory cells are grouped and controlled in NAND strings of 64 cells aligned in parallel, double the number of 56nm devices, with a dummy word-line cell at either end to prevent program disturbance. This technology contributes to reduce the number of select gates and to improve memory area efficiency, according to the company. Modification of the peripheral circuit design also contributes to reduced chip area. The addition of high-voltage switches to the circuit reduces the number of control-gate driver circuits required to drive word lines, and ground buses are routed on the memory cell arrays.

Toshiba has started shipments of commercial samples of new 16Gbit (2Gbyte) single-chip, multilevel cell (MLC) NAND flash memories, the current mainstream density, and will start mass production in March. The company intends to start mass production of 32Gbit (4Gbyte) NAND flash memories early in Q3. The new chips will be produced at Fab 4, the latest 300mm wafer fabrication facility at Toshiba's Yokkaichi Operations, in Mie prefecture, Japan.

Comment on "16Gbit NAND fabricated with 43nm tec..."
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top