Global Sources
EE Times-India
Stay in touch with EE Times India
EE Times-India > Processors/DSPs

Simulating and debugging multi-core behaviour

Posted: 04 Mar 2006     Print Version  Bookmark and Share

Keywords:multi-core processor  processor chips  debugger 

Multi-core microprocessor chips are on their way, and they're going to further complicate the task facing embedded software developers. Of course, multi-processor systems aren't new. Chips with multiple heterogeneous (different) processors, such as a RISC and a DSP, have been around for years. In fact, nearly every modern cell phone contains just such a pair.

What's new is that the number of microprocessors is dramatically increasing in order to handle the equally dramatic increase in system-on-a-chip (SoC) software content, and that these processors generally share cache memory. This approach, known as shared-memory multi-processing or symmetric multi-processing (SMP), adds a whole new level of complexity because software will normally need to be dynamically partitioned across the processors. Traditional static partitioning won't work.

View the PDF document for more information.

Comment on "Simulating and debugging multi-core ..."
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top