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Via unveils 64bit x86-based MCU

Posted: 28 Jan 2008     Print Version  Bookmark and Share

Keywords:Via Technologies  Isaiah Architecture  processor 64bit 

Taiwan's Via Technologies Inc. introduces its latest x86-based microprocessor—a 64bit chip built around a 65nm process.

The company's so-called Via Isaiah Architecture is said to pave the way for new, low-power systems. Designed by the company's U.S.-based processor design subsidiary, Centaur Technology Inc., the Via Isaiah Architecture is a 64bit superscalar, speculative out-of-order microarchitecture.

Also based on a new virtual machine architecture, the first-generation of Isaiah-based products will be pin-compatible with the Via's current C7 processor family. The first processors implementing the Via Isaiah Architecture will use 65nm technology.

''With a team of less than one hundred engineers, we have created from scratch the world's most power-efficient x86 processor architecture,'' said Glenn Henry, president of Centaur. The technology ''will enable us to further extend our growing presence in the global x86 processor market,'' added Wenchi Chen, president and CEO of Via.

At present, Via has a small share of the x86-based processor market. It is a bigger player in the PC chipset business.

Bigger share
However, the tide may be changing for Via. Wal-Mart has been selling a hot, Linux-based PC. Wal-Mart began selling the Everex gPC online for Rs.7,856.20 ($199). The system is based on a processor from Via.

To gain a bigger share of the overall market, Via said that the Via Isaiah Architecture has been optimised to meet the demand for smaller and more functional systems, including mobile and desktop platforms.

Taking a page from rival x86-based processors, the Via Isaiah Architecture features a superscalar and an out of order architecture with branch prediction. Supporting clock speeds of up to 2GHz in initial products and a front side bus scalable from 800-1,333MHz, the Via Isaiah Architecture also features two 64KByte L1 caches and 1MByte of L2 cache with 16-way associativity.

It also integrates a floating point unit (FPU) said to execute four floating point adds and four multiplies per clock. Support for new SSE instructions and a 128bit wide integer data path further boost multimedia performance, according to Via.

It utilises new low-power circuit techniques, which supports its so-called ''C6'' power state technology. Via's Adaptive PowerSaver Technology is said to further reduce power consumption, according to the company. Processors implementing the VIA Isaiah Architecture are expected to start shipping in 1H 08.

- Mark LaPedus
EE Times

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