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High-speed ADCs bridge analogue, digital hardware

Posted: 16 Jan 2007     Print Version  Bookmark and Share

Keywords:programmability  digital hardware  analog  versatile high-speed ADCs  design high-speed ADCs 

For many years, the typical pipeline architecture used by ADCs in high-speed signal conversion systems contained all of the functions needed to sample a waveform integrated into one package:

• Some form of track-and-hold circuit to hold the signal for conversion;

• Built-in reference and bias currents;

• Clock buffers and minor digital circuitry to arrange the bits from the various stages into an error-free data word.

For the most part, programmability in these converters was limited to turning on/off the converter via a sleep pin, or by selecting either two's complement or offset binary output format.

With the speed and channel density of ADCs increasing, in-system adjustments to digital output-drive levels and termination resistors can aid the digital signal integrity at high data rates. This is especially true for ADCs with a serial LVDS output. Training patterns can be sent over the output bus by providing a digital stimulus from the ADC outputs in the absence of an input signal. This ensures that the digital components are properly connected. Even performance trade-offs between SNR and spurious-free dynamic range (SFDR) can be made with register adjustments.

An example of increased programmability in a pipeline ADC is the ADS644. The device has four 14bit, 125MSps ADCs integrated into one 9-by-9mm package, as well as user programmability, thus making it easier to use than multiple ADCs each containing a single converter, in a larger total footprint. Many features are available to fine-tune the digital interface, as well as make system tradeoffs between SNR and SFDR. This is where the true value of the in-system programmability exists.

Once the link between the ADC and the digital device downstream is defined and built on a board, the ability to adjust the ADC via the serial programmable interface (SPI) could reduce to 5mins what previously would take several weeks of debugging. Without this programmability, multiple board design spins may have been required to fix any unexpected digital signal integrity or timing issues.

Adjustable LVDS interface
The adjustable LVDS current levels available in the register settings via the SPI in the ADS6445 allow differential signal integrity for low impedance or poorly matched interconnects to be optimised. These adjustments can be made after the board is fabricated. The LVDS signal integrity is characterised at the end of the LVDS transmission path.

For instance, Figure 1a is an oscilloscope plot of one LVDS data output bit with only 5pF of loading capacitance. The LVDS output drive strength is set to 3.5mA into 100Ω on the board, toggling at ~375MHz. These are normal LVDS settings. At high speeds and over long distances, reflections may occur in the LVDS signal that degrade the data valid window and corrupt the receiving device's ability to discern a proper transition. Such signal integrity issues are beginning to occur in the figure.

Several options exist for solving this problem. None of them require anything more than access to the ADC SPI. You can select an internal load resistor in the LVDS output as a source load to terminate the transmission line. That creates a 50Ω load to the LVDS output (two 100Ω resistors in parallel). Therefore, the nominal 3.5mA current creates a signal half the nominal output voltage of 700mVpp.

The lower differential signal level could in itself cause as many detection errors as the previously degraded signal, but it would be fine for many systems, provided the LVDS receiver has the required sensitivity.

If a higher LVDS swing is required, the ADS6445 can be instructed to double the LVDS output current to 7mA (Figure 1b), putting the signal back to 700mVpp. The capacitive load is doubled from 5pF to 10pF to exaggerate the benefit of the extra current and double termination. All of the transitions are now consistent with no reflected energy.

Figure 1: LVDS loading at 5pF with nominal 3.5mA into 100Ω load (left) and at 10pF with 7mA into 50Ω load (right).

Just as the drive strength can be increased as needed, it can be decreased when the LVDS signal integrity allows, thus saving power. To save power, if the full 700mVpp is deemed unnecessary, or there is a situation where perhaps the distance is short and the loading small between the ADC and the digital device, then alternate LVDS output currents and load resistors are available.

These create several benefits, depending on the desired result. In the case where the signal rate is not extremely high and the capacitive loading is low, you can use one of several current settings below the 3.5mA standard and an internal load resistor that is larger than 100Ω (no external load resistor is even required, which saves money and space), and still create a reliable link.

An example of power savings, when the signal integrity allows it, is to select a 142Ω internal LVDS differential load and 2.5mA of LVDS current. With this combination, you will still achieve approximately 700mVpp. Generally, it is recommended to provide a footprint for a differential-termination resistor at the end of the LVDS path, in case the conditions warrant it. It may be unnecessary for short paths, and the internal source termination resistors inside the ADC will be sufficient.

Drive strength
LVDS specifications allow the differential output of the LVDS source to be anywhere from 247mV to 454mV peak. Other combinations are possible for increasing or decreasing the LVDS drive strength and voltage levels that are still within the TIA/EIA/ANSI-644 LVDS specification. You can select these features from the beginning of system concept to save power. Alternatively, they can be used simply as insurance in the event LVDS signal integrity issues are unexpectedly discovered.

These features have the potential to save a great deal of time and money in board debug should issues arise. Look carefully at the voltage levels required by the LVDS receiving device. Because every board is different, you may need to program the ADC to adjust the LVDS output levels. This is to maintain the allowable range at the LVDS receiver after board signal losses are characterised and taken into account.

Built-in test patterns
The ADS6445 provides several built-in test patterns that can be enabled in the absence of an analogue input source. These can be used during initial board debug to study the timing relationship between the ADC and the FPGA, in order to determine the proper clock-to-data relationship at the FPGA interface. This ensures good timing. Typically, timing can be adjusted within the FPGA LVDS inputs.

One benefit of using a built-in training pattern, compared with supplying an analogue signal, is that the pattern is consistent. This eliminates any question of error coming from the analogue source, making the experiment repeatable and easier to set up. The training pattern can also be used as part of a board functionality test during board manufacturing and testing.

Signal gain, SNR, SFDR
Programmability can do more than solve board-level interconnect issues. Some features are designed to allow system performance tradeoffs. For instance, the ADS6445 also has internal analogue-input signal-gain functions that allow you to tradeoff SNR for improved SFDR, or simply to lower the analogue-input amplitude. A smaller input signal usually provides better distortion from the analogue components prior to the ADC and within the ADC itself.

Figure 2a: SFDR vs. input frequency using fine gain control.

Figure 2b: SFDR vs. input frequency using coarse gain control.

The ADS6445 contains both coarse and fine gain options. In either case, the analogue-input voltage level must be reduced by at least the amount of gain selected in the ADC. This keeps the ADC's input voltage range from saturating and clipping the digital output word. Therefore, if you want to explore using the gain settings in the ADC, plan to reduce the analogue input-signal levels at the board level in the analogue circuits prior to the ADC.

In Figure 2, the tradeoffs are visible between input signal level and distortion (or specifically stated here as SFDR) using two different gain-adjustment methods. This feature can be used to achieve multiple objectives. Depending on the input frequency of interest, SFDR can be improved at the expense of SNR in the converter for narrowband systems that can recover the SNR using digital decimation. Moreover, by allowing smaller input signals to be driven into the ADC while still maintaining the full-scale codes from the ADC, the analogue circuitry driving the ADC likely will have improved distortion as well, creating better SFDR for the amplifier plus ADC combined.

You can use this feature during prototyping to determine the optimum combination of input signal level for best distortion of the system without designing multiple boards. The gain adjustment could be used dynamically in the system, in combination with an automatic gain control (AGC), to recover as much dynamic range as possible. The coarse 3.5dB gain setting is also available via a package pin for applications that wish to adjust the ADC gain without the SPI, as is a subset of additional internal registers.

Figure 3 and Figure 4 indicate the reduction in SNR and distortion (SINAD) and SNR associated with the internal gain settings of the ADC.

Figure 3: SINAD vs. input frequency using fine gain control.

Figure 4: SNR vs. input frequency using coarse gain control.

As high-speed ADCs become more programmable, they become more user-friendly. For the traditional analogue-hardware designer who cringes at the idea of an SPI or other method of programming a component in the system, the ADC still can be used with the default settings and the programmability feature simply ignored.

The high-speed ADC is the bridge between the analogue and digital hardware, and many times it is placed in the responsibility of an all-digital or all-analogue hardware designer. When that happens, the programmability has easier acceptance with the digital hardware designer, but it can save the day for an analogue hardware designer who failed to set up the digital timing or signal integrity properly.

In addition to the quad ADC, dual and single converters are available with similar programmability in the same family. More information is available at and

- Philip M. Pratt
Systems Engineer, Texas Instruments Inc.

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