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EE Times-India > EDA/IP

Modelling for accurate Serdes design

Posted: 16 Dec 2007     Print Version  Bookmark and Share

Keywords:Serdes I/O  advanced PCB systems  serial links  BIRD 104 

To ensure that the serial link is designed at the board level, systems companies must either simulate serial links with models of Serdes transceivers or build a fully functional physical prototype of the system. Simulation is preferred over building physical prototypes to reduce costs and to shorten design cycle time.

Algorithmic modelling methodology gives designers flexibility in modelling their device accurately while providing them with all the IP protection they need. It brings a revolutionary change in which complex multi-gigabit transceivers can be modelled for high-speed I/O circuits. Backed by multiple EDA vendors and IP companies, this technology will give systems companies interoperability and the ability to simulate huge bit stream to predict BER without the need to build physical prototypes.

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